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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e58542f3sm279837095e9.10.2025.08.11.23.11.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 23:11:10 -0700 (PDT) Message-ID: <0a422178-d251-4d28-b355-c617b588d486@linaro.org> Date: Tue, 12 Aug 2025 08:11:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 50/85] target/arm: Expand pstate to 64 bits To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier , =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20250802232953.413294-1-richard.henderson@linaro.org> <20250802232953.413294-51-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250802232953.413294-51-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/8/25 01:29, Richard Henderson wrote: > The ARM now defines 36 bits in SPSR_ELx in aarch64 mode, so > it's time to bite the bullet and extend PSTATE to match. > > Most changes are straightforward, adjusting printf formats, > changing local variable types. More complex is migration, > where to maintain backward compatibility a new pstate64 > record is introduced, and only when one of the extensions > that sets bits 32-35 are active. > > The fate of gdbstub is left undecided for the moment. > > Reviewed-by: Pierrick Bouvier > Signed-off-by: Richard Henderson > --- > target/arm/cpu.h | 8 +++--- > target/arm/tcg/translate.h | 20 ++++++------- > target/arm/cpu.c | 6 ++-- > target/arm/gdbstub64.c | 1 + > target/arm/helper.c | 11 ++++---- > target/arm/machine.c | 56 +++++++++++++++++++++++++++++++++++++ > target/arm/tcg/helper-a64.c | 2 +- > 7 files changed, 81 insertions(+), 23 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 98360b70b8..7769c4ae3c 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -268,7 +268,7 @@ typedef struct CPUArchState { > uint64_t xregs[32]; > uint64_t pc; > /* PSTATE isn't an architectural register for ARMv8. However, it is > - * convenient for us to assemble the underlying state into a 32 bit format > + * convenient for us to assemble the underlying state into a 64 bit format > * identical to the architectural format used for the SPSR. (This is also > * what the Linux kernel's 'pstate' field in signal handlers and KVM's > * 'pstate' register are.) Of the PSTATE bits: > @@ -280,7 +280,7 @@ typedef struct CPUArchState { > * SM and ZA are kept in env->svcr > * all other bits are stored in their correct places in env->pstate > */ > - uint32_t pstate; > + uint64_t pstate; > bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ > bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ > diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c > index 64ee9b3b56..3cef47281a 100644 > --- a/target/arm/gdbstub64.c > +++ b/target/arm/gdbstub64.c > @@ -47,6 +47,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > case 32: > return gdb_get_reg64(mem_buf, env->pc); > case 33: > + /* pstate is now a 64-bit value; can we simply adjust the xml? */ Please add a similar comment in aarch64_cpu_gdb_write_register(), to not forget to update the returned value (4 -> 8) when XML gets adjusted. > return gdb_get_reg32(mem_buf, pstate_read(env)); > } > /* Unknown register. */