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[212.78.193.212]) by smtp.gmail.com with ESMTPSA id w10-20020aa7dcca000000b005309eb7544fsm619392edu.45.2023.09.21.03.11.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Sep 2023 03:11:01 -0700 (PDT) Message-ID: <0a4b2ef4-8184-b887-af8a-542315e671fb@linaro.org> Date: Thu, 21 Sep 2023 12:10:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] amd_iommu: Fix APIC address check Content-Language: en-US To: Akihiko Odaki Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Paolo Bonzini , Peter Xu References: <20230909162355.384982-1-akihiko.odaki@daynix.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230909162355.384982-1-akihiko.odaki@daynix.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Akihiko, Adding Peter. On 9/9/23 18:23, Akihiko Odaki wrote: > An MSI from I/O APIC may not exactly equal to APIC_DEFAULT_ADDRESS. In > fact, Windows 17763.3650 configures I/O APIC to set the dest_mode bit. > Check only the 12 bits that are known to be fixed for I/O APIC-generated > MSIs. > > Fixes: 577c470f43 ("x86_iommu/amd: Prepare for interrupt remap support") > Signed-off-by: Akihiko Odaki > --- > hw/i386/amd_iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 4655cd801f..3ac0d0098d 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -1268,7 +1268,7 @@ static int amdvi_int_remap_msi(AMDVIState *iommu, > return -AMDVI_IR_ERR; > } > > - if ((origin->address & AMDVI_MSI_ADDR_LO_MASK) != APIC_DEFAULT_ADDRESS) { > + if ((origin->address & 0xfff00000) != APIC_DEFAULT_ADDRESS) { > trace_amdvi_err("MSI is not from IOAPIC."); > return -AMDVI_IR_ERR; > } Could you add a definition? Maybe: -- >8 -- diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 6da893ee57..85d491e585 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -210,6 +210,7 @@ #define AMDVI_INT_ADDR_FIRST 0xfee00000 #define AMDVI_INT_ADDR_LAST 0xfeefffff #define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1) +#define AMDVI_INT_ADDR_MASK ~(AMDVI_INT_ADDR_SIZE - 1) #define AMDVI_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) #define AMDVI_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9c77304438..093b4fb18f 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1252,7 +1252,7 @@ static int amdvi_int_remap_msi(AMDVIState *iommu, return -AMDVI_IR_ERR; } - if ((origin->address & AMDVI_MSI_ADDR_LO_MASK) != APIC_DEFAULT_ADDRESS) { + if ((origin->address & AMDVI_INT_ADDR_MASK) != APIC_DEFAULT_ADDRESS) { trace_amdvi_err("MSI is not from IOAPIC."); return -AMDVI_IR_ERR; } --- ?