From: Richard Henderson <richard.henderson@linaro.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH] RISC-V: Add support for Ztso
Date: Sat, 17 Sep 2022 10:02:46 +0200 [thread overview]
Message-ID: <0a809729-26ad-5d71-b849-cf008ece4a87@linaro.org> (raw)
In-Reply-To: <mhng-5d39306a-7bd0-493f-8364-5ae9e921ec97@palmer-ri-x1c9>
On 9/16/22 14:52, Palmer Dabbelt wrote:
>> Though, honestly, I've had patches to add the required barriers sitting around for the
>> last few releases, to better support things like x86 on aarch64. I should just finish
>> that up.
>
> I can just do that for the RISC-V TSO support? Like the cover letter says that was my
> first thought, it's only when I found the comment saying not to do it that I went this way.
My patches inject the barriers automatically by the tcg optimizer, rather than by hand,
which is what the comment was trying to discourage. Last version was
https://lore.kernel.org/qemu-devel/20210316220735.2048137-1-richard.henderson@linaro.org/
r~
next prev parent reply other threads:[~2022-09-17 8:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-02 3:44 [PATCH] RISC-V: Add support for Ztso Palmer Dabbelt
2022-09-04 0:47 ` Richard Henderson
2022-09-16 12:52 ` Palmer Dabbelt
2022-09-17 8:02 ` Richard Henderson [this message]
2022-09-17 8:22 ` Palmer Dabbelt
2022-09-29 19:16 ` Dr. David Alan Gilbert
2022-10-02 21:20 ` Palmer Dabbelt
2022-10-03 8:44 ` Dr. David Alan Gilbert
2022-10-13 9:18 ` Andrea Parri
2022-10-13 9:59 ` Dr. David Alan Gilbert
2022-10-13 10:25 ` Andrea Parri
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