From: Richard Henderson <rth@twiddle.net>
To: Kirill Batuzov <batuzovk@ispras.ru>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type
Date: Mon, 23 Jan 2017 10:43:31 -0800 [thread overview]
Message-ID: <0b0b1136-ada6-f30e-a6b9-90263d55e7da@twiddle.net> (raw)
In-Reply-To: <alpine.DEB.2.11.1701231246360.2026@bulbul.intra.ispras.ru>
On 01/23/2017 02:30 AM, Kirill Batuzov wrote:
> Because 4 adds on 4 i32 registers work good only when the size of
> vector elements matches the size of scalar variables we use for
> representation of a vector. add_i16x8 will not be that great if we use
> 4 i32 variables: each will need to be split into two values, processed
> independently and merged back afterwards.
Certainly. But that's pretty much exactly how they are processed now. Usually
via a helper function that accepts an i64 input as a pair of i32 arguments.
> Scalar variables lack primitives to work with them as vectors of shorter
> values. This is one of the reasons I added v64 type instead of using i64
> for 64-bit vector operations. And this is the reason I'm so opposed to
> using them to represent vector types if vector registers are not
> supported by host. Handling vector operations with element size that
> does not match representation will be complicated, may require special
> handling for different operations and will produce a lot of if-s in code.
A lot of if's? I've no idea what you're talking about.
A v64 type makes sense because generally we're going to allocate them to a
different register set than i64. That said, i64 is perfectly adequate for
implementing add_i8x8:
t0 = in1 & 0x7f7f7f7f7f7f7f7f
t1 = in0 + t0;
t2 = in1 & 0x8080808080808080
out = t1 ^ t2
This is less expensive than addition by pieces if there are at least 4 pieces.
> The method I'm proposing can handle any operation regardless of
> representation. This includes handling situation where host supports
> vector registers but does not support required operation (for example
> SSE/AVX does not support multiplication of vectors of 8-bit values).
Not for nothing but it's trivial to expand with punpcklbw, punpckhbw, pmullw,
pand, packuswb. That said, if an expansion gets too complicated, it's still
better to move it into a helper than expand 16 * (load, op, store).
r~
next prev parent reply other threads:[~2017-01-23 18:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-17 9:07 [Qemu-devel] [PATCH 00/18] Emulate guest vector operations with host vector operations Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 01/18] tcg: add support for 128bit vector type Kirill Batuzov
2017-01-18 18:29 ` Richard Henderson
2017-01-19 13:04 ` Kirill Batuzov
2017-01-19 15:09 ` Richard Henderson
2017-01-19 16:54 ` Kirill Batuzov
2017-01-22 7:00 ` Richard Henderson
2017-01-23 10:30 ` Kirill Batuzov
2017-01-23 18:43 ` Richard Henderson [this message]
2017-01-24 14:29 ` Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 02/18] tcg: add support for 64bit " Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 03/18] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 04/18] tcg: add simple alias analysis Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 05/18] tcg: use results of alias analysis in liveness analysis Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 06/18] tcg: allow globals to overlap Kirill Batuzov
2017-01-17 19:50 ` Richard Henderson
2017-01-17 9:07 ` [Qemu-devel] [PATCH 07/18] tcg: add vector addition operations Kirill Batuzov
2017-01-17 21:56 ` Richard Henderson
2017-01-17 9:07 ` [Qemu-devel] [PATCH 08/18] target/arm: support access to vector guest registers as globals Kirill Batuzov
2017-01-17 20:07 ` Richard Henderson
2017-01-17 9:07 ` [Qemu-devel] [PATCH 09/18] target/arm: use vector opcode to handle vadd.<size> instruction Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 10/18] tcg/i386: add support for vector opcodes Kirill Batuzov
2017-01-17 20:19 ` Richard Henderson
2017-01-18 13:05 ` Kirill Batuzov
2017-01-18 18:22 ` Richard Henderson
2017-01-27 14:51 ` Alex Bennée
2017-01-17 9:07 ` [Qemu-devel] [PATCH 11/18] tcg/i386: support 64-bit vector operations Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 12/18] tcg/i386: support remaining vector addition operations Kirill Batuzov
2017-01-17 21:49 ` Richard Henderson
2017-01-17 9:07 ` [Qemu-devel] [PATCH 13/18] tcg: do not relay on exact values of MO_BSWAP or MO_SIGN in backend Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 14/18] tcg: introduce new TCGMemOp - MO_128 Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 15/18] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 16/18] softmmu: create helpers for vector loads Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 17/18] tcg/i386: add support for qemu_ld_v128/qemu_st_v128 ops Kirill Batuzov
2017-01-17 9:07 ` [Qemu-devel] [PATCH 18/18] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg Kirill Batuzov
2017-01-27 14:55 ` [Qemu-devel] [PATCH 00/18] Emulate guest vector operations with host vector operations Alex Bennée
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