* [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
@ 2023-03-05 9:42 Jim Shu
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Jim Shu @ 2023-03-05 9:42 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Jim Shu, Alex Bennée, Philippe Mathieu-Daudé,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
This patch enables a debugger to read current virtualization mode via
virtual "virt" register. After it, we could get full current privilege
mode via both "priv" and "virt" register.
Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
support H-extension.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
gdb-xml/riscv-32bit-virtual.xml | 1 +
gdb-xml/riscv-64bit-virtual.xml | 1 +
target/riscv/gdbstub.c | 12 ++++++++----
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml
index 905f1c555d..d44b6ca2dc 100644
--- a/gdb-xml/riscv-32bit-virtual.xml
+++ b/gdb-xml/riscv-32bit-virtual.xml
@@ -8,4 +8,5 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.virtual">
<reg name="priv" bitsize="32"/>
+ <reg name="virt" bitsize="32"/>
</feature>
diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml
index 62d86c237b..7c9b63d5b6 100644
--- a/gdb-xml/riscv-64bit-virtual.xml
+++ b/gdb-xml/riscv-64bit-virtual.xml
@@ -8,4 +8,5 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.virtual">
<reg name="priv" bitsize="64"/>
+ <reg name="virt" bitsize="64"/>
</feature>
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 6048541606..1755fd9d51 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -187,13 +187,17 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
{
- if (n == 0) {
#ifdef CONFIG_USER_ONLY
+ if (n >= 0 && n <= 1) {
return gdb_get_regl(buf, 0);
+ }
#else
+ if (n == 0) {
return gdb_get_regl(buf, cs->priv);
-#endif
+ } else if (n == 1) {
+ return gdb_get_regl(buf, riscv_cpu_virt_enabled(cs));
}
+#endif
return 0;
}
@@ -328,13 +332,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
- 1, "riscv-32bit-virtual.xml", 0);
+ 2, "riscv-32bit-virtual.xml", 0);
break;
case MXL_RV64:
case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
+ 2, "riscv-64bit-virtual.xml", 0);
break;
default:
g_assert_not_reached();
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-05 9:42 [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads Jim Shu
@ 2023-03-05 9:42 ` Jim Shu
2023-03-06 11:26 ` LIU Zhiwei
2023-03-10 3:58 ` Alistair Francis
2023-03-06 11:22 ` [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads LIU Zhiwei
2023-03-10 0:05 ` Alistair Francis
2 siblings, 2 replies; 9+ messages in thread
From: Jim Shu @ 2023-03-05 9:42 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Jim Shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
This patch also enables debugger to set current privilege mode to
VU/VS-mode.
Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
support H-extension.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/gdbstub.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1755fd9d51..a7f234beaf 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
{
+#ifdef CONFIG_USER_ONLY
+ if (n >= 0 && n <= 1) {
+ return sizeof(target_ulong);
+ }
+#else
+ bool virt;
+
if (n == 0) {
-#ifndef CONFIG_USER_ONLY
cs->priv = ldtul_p(mem_buf) & 0x3;
if (cs->priv == PRV_H) {
cs->priv = PRV_S;
}
-#endif
+ return sizeof(target_ulong);
+ } else if (n == 1) {
+ virt = ldtul_p(mem_buf) & 0x1;
+ if ((cs->priv == PRV_M) && (virt == true)) {
+ /* M-mode only supports V=0. */
+ virt = false;
+ }
+ riscv_cpu_set_virt_enabled(cs, virt);
return sizeof(target_ulong);
}
+#endif
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
@ 2023-03-06 11:26 ` LIU Zhiwei
2023-03-08 11:14 ` Jim Shu
2023-03-09 3:05 ` Jim Shu
2023-03-10 3:58 ` Alistair Francis
1 sibling, 2 replies; 9+ messages in thread
From: LIU Zhiwei @ 2023-03-06 11:26 UTC (permalink / raw)
To: Jim Shu, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza
On 2023/3/5 17:42, Jim Shu wrote:
> This patch also enables debugger to set current privilege mode to
> VU/VS-mode.
>
> Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> support H-extension.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/gdbstub.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 1755fd9d51..a7f234beaf 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
>
> static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
> {
> +#ifdef CONFIG_USER_ONLY
> + if (n >= 0 && n <= 1) {
> + return sizeof(target_ulong);
> + }
> +#else
> + bool virt;
> +
> if (n == 0) {
> -#ifndef CONFIG_USER_ONLY
> cs->priv = ldtul_p(mem_buf) & 0x3;
> if (cs->priv == PRV_H) {
> cs->priv = PRV_S;
> }
> -#endif
> + return sizeof(target_ulong);
We should return according to the misa_mxl_max. And this is a bug before
your commit.
> + } else if (n == 1) {
> + virt = ldtul_p(mem_buf) & 0x1;
> + if ((cs->priv == PRV_M) && (virt == true)) {
> + /* M-mode only supports V=0. */
> + virt = false;
> + }
> + riscv_cpu_set_virt_enabled(cs, virt);
> return sizeof(target_ulong);
Same error here. Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> }
> +#endif
> return 0;
> }
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-06 11:26 ` LIU Zhiwei
@ 2023-03-08 11:14 ` Jim Shu
2023-03-09 3:05 ` Jim Shu
1 sibling, 0 replies; 9+ messages in thread
From: Jim Shu @ 2023-03-08 11:14 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza
Thanks for reviewing.
I'll fix this issue.
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
>
> On 2023/3/5 17:42, Jim Shu wrote:
> > This patch also enables debugger to set current privilege mode to
> > VU/VS-mode.
> >
> > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> > support H-extension.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/gdbstub.c | 18 ++++++++++++++++--
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> > index 1755fd9d51..a7f234beaf 100644
> > --- a/target/riscv/gdbstub.c
> > +++ b/target/riscv/gdbstub.c
> > @@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
> >
> > static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
> > {
> > +#ifdef CONFIG_USER_ONLY
> > + if (n >= 0 && n <= 1) {
> > + return sizeof(target_ulong);
> > + }
> > +#else
> > + bool virt;
> > +
> > if (n == 0) {
> > -#ifndef CONFIG_USER_ONLY
> > cs->priv = ldtul_p(mem_buf) & 0x3;
> > if (cs->priv == PRV_H) {
> > cs->priv = PRV_S;
> > }
> > -#endif
> > + return sizeof(target_ulong);
> We should return according to the misa_mxl_max. And this is a bug before
> your commit.
> > + } else if (n == 1) {
> > + virt = ldtul_p(mem_buf) & 0x1;
> > + if ((cs->priv == PRV_M) && (virt == true)) {
> > + /* M-mode only supports V=0. */
> > + virt = false;
> > + }
> > + riscv_cpu_set_virt_enabled(cs, virt);
> > return sizeof(target_ulong);
> Same error here. Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Zhiwei
>
> > }
> > +#endif
> > return 0;
> > }
> >
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-06 11:26 ` LIU Zhiwei
2023-03-08 11:14 ` Jim Shu
@ 2023-03-09 3:05 ` Jim Shu
2023-03-09 3:21 ` LIU Zhiwei
1 sibling, 1 reply; 9+ messages in thread
From: Jim Shu @ 2023-03-09 3:05 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
>
> On 2023/3/5 17:42, Jim Shu wrote:
> > This patch also enables debugger to set current privilege mode to
> > VU/VS-mode.
> >
> > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> > support H-extension.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/gdbstub.c | 18 ++++++++++++++++--
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> > index 1755fd9d51..a7f234beaf 100644
> > --- a/target/riscv/gdbstub.c
> > +++ b/target/riscv/gdbstub.c
> > @@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
> >
> > static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
> > {
> > +#ifdef CONFIG_USER_ONLY
> > + if (n >= 0 && n <= 1) {
> > + return sizeof(target_ulong);
> > + }
> > +#else
> > + bool virt;
> > +
> > if (n == 0) {
> > -#ifndef CONFIG_USER_ONLY
> > cs->priv = ldtul_p(mem_buf) & 0x3;
> > if (cs->priv == PRV_H) {
> > cs->priv = PRV_S;
> > }
> > -#endif
> > + return sizeof(target_ulong);
> We should return according to the misa_mxl_max. And this is a bug before
> your commit.
Hi Zhiwei,
After reading other gdbstub.c code, I think it is OK to use
'sizeof(target_ulong)' as virtual register length.
Its length is 32-bit in RV32 and is 64-bit in RV64/RV128. We don't
need to handle RV128 specially.
Virtual register length is same as CSR length and
'riscv_gdb_set_csr()' also use 'sizeof(target_ulong)'.
Jim Shu
> > + } else if (n == 1) {
> > + virt = ldtul_p(mem_buf) & 0x1;
> > + if ((cs->priv == PRV_M) && (virt == true)) {
> > + /* M-mode only supports V=0. */
> > + virt = false;
> > + }
> > + riscv_cpu_set_virt_enabled(cs, virt);
> > return sizeof(target_ulong);
> Same error here. Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Zhiwei
>
> > }
> > +#endif
> > return 0;
> > }
> >
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-09 3:05 ` Jim Shu
@ 2023-03-09 3:21 ` LIU Zhiwei
0 siblings, 0 replies; 9+ messages in thread
From: LIU Zhiwei @ 2023-03-09 3:21 UTC (permalink / raw)
To: Jim Shu
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza
On 2023/3/9 11:05, Jim Shu wrote:
> On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>>
>> On 2023/3/5 17:42, Jim Shu wrote:
>>> This patch also enables debugger to set current privilege mode to
>>> VU/VS-mode.
>>>
>>> Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
>>> support H-extension.
>>>
>>> Signed-off-by: Jim Shu <jim.shu@sifive.com>
>>> Reviewed-by: Frank Chang <frank.chang@sifive.com>
>>> ---
>>> target/riscv/gdbstub.c | 18 ++++++++++++++++--
>>> 1 file changed, 16 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
>>> index 1755fd9d51..a7f234beaf 100644
>>> --- a/target/riscv/gdbstub.c
>>> +++ b/target/riscv/gdbstub.c
>>> @@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
>>>
>>> static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
>>> {
>>> +#ifdef CONFIG_USER_ONLY
>>> + if (n >= 0 && n <= 1) {
>>> + return sizeof(target_ulong);
>>> + }
>>> +#else
>>> + bool virt;
>>> +
>>> if (n == 0) {
>>> -#ifndef CONFIG_USER_ONLY
>>> cs->priv = ldtul_p(mem_buf) & 0x3;
>>> if (cs->priv == PRV_H) {
>>> cs->priv = PRV_S;
>>> }
>>> -#endif
>>> + return sizeof(target_ulong);
>> We should return according to the misa_mxl_max. And this is a bug before
>> your commit.
> Hi Zhiwei,
>
> After reading other gdbstub.c code, I think it is OK to use
> 'sizeof(target_ulong)' as virtual register length.
No, you should refer to the riscv_cpu_gdb_read(write)_register.
> Its length is 32-bit in RV32 and is 64-bit in RV64/RV128.
Although we don't support MXLEN 32bit currently on qemu-system-riscv64,
we should not introduce more code
to make dynamic xlen support complex.
Zhiwei
> We don't
> need to handle RV128 specially.
> Virtual register length is same as CSR length and
> 'riscv_gdb_set_csr()' also use 'sizeof(target_ulong)'.
>
> Jim Shu
>
>>> + } else if (n == 1) {
>>> + virt = ldtul_p(mem_buf) & 0x1;
>>> + if ((cs->priv == PRV_M) && (virt == true)) {
>>> + /* M-mode only supports V=0. */
>>> + virt = false;
>>> + }
>>> + riscv_cpu_set_virt_enabled(cs, virt);
>>> return sizeof(target_ulong);
>> Same error here. Otherwise,
>>
>> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>>
>> Zhiwei
>>
>>> }
>>> +#endif
>>> return 0;
>>> }
>>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
2023-03-06 11:26 ` LIU Zhiwei
@ 2023-03-10 3:58 ` Alistair Francis
1 sibling, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2023-03-10 3:58 UTC (permalink / raw)
To: Jim Shu
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
On Sun, Mar 5, 2023 at 7:43 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch also enables debugger to set current privilege mode to
> VU/VS-mode.
>
> Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
> support H-extension.
I'm not sure we want this. What is the use case for this?
Changing the virt mode on the fly like this is likely to break lots of
software. Should we really allow users to do this?
Alistair
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/gdbstub.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 1755fd9d51..a7f234beaf 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -203,15 +203,29 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
>
> static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
> {
> +#ifdef CONFIG_USER_ONLY
> + if (n >= 0 && n <= 1) {
> + return sizeof(target_ulong);
> + }
> +#else
> + bool virt;
> +
> if (n == 0) {
> -#ifndef CONFIG_USER_ONLY
> cs->priv = ldtul_p(mem_buf) & 0x3;
> if (cs->priv == PRV_H) {
> cs->priv = PRV_S;
> }
> -#endif
> + return sizeof(target_ulong);
> + } else if (n == 1) {
> + virt = ldtul_p(mem_buf) & 0x1;
> + if ((cs->priv == PRV_M) && (virt == true)) {
> + /* M-mode only supports V=0. */
> + virt = false;
> + }
> + riscv_cpu_set_virt_enabled(cs, virt);
> return sizeof(target_ulong);
> }
> +#endif
> return 0;
> }
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
2023-03-05 9:42 [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads Jim Shu
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
@ 2023-03-06 11:22 ` LIU Zhiwei
2023-03-10 0:05 ` Alistair Francis
2 siblings, 0 replies; 9+ messages in thread
From: LIU Zhiwei @ 2023-03-06 11:22 UTC (permalink / raw)
To: Jim Shu, qemu-devel, qemu-riscv
Cc: Alex Bennée, Philippe Mathieu-Daudé, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza
On 2023/3/5 17:42, Jim Shu wrote:
> This patch enables a debugger to read current virtualization mode via
> virtual "virt" register. After it, we could get full current privilege
> mode via both "priv" and "virt" register.
>
> Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
> support H-extension.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> gdb-xml/riscv-32bit-virtual.xml | 1 +
> gdb-xml/riscv-64bit-virtual.xml | 1 +
> target/riscv/gdbstub.c | 12 ++++++++----
> 3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml
> index 905f1c555d..d44b6ca2dc 100644
> --- a/gdb-xml/riscv-32bit-virtual.xml
> +++ b/gdb-xml/riscv-32bit-virtual.xml
> @@ -8,4 +8,5 @@
> <!DOCTYPE feature SYSTEM "gdb-target.dtd">
> <feature name="org.gnu.gdb.riscv.virtual">
> <reg name="priv" bitsize="32"/>
> + <reg name="virt" bitsize="32"/>
> </feature>
> diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml
> index 62d86c237b..7c9b63d5b6 100644
> --- a/gdb-xml/riscv-64bit-virtual.xml
> +++ b/gdb-xml/riscv-64bit-virtual.xml
> @@ -8,4 +8,5 @@
> <!DOCTYPE feature SYSTEM "gdb-target.dtd">
> <feature name="org.gnu.gdb.riscv.virtual">
> <reg name="priv" bitsize="64"/>
> + <reg name="virt" bitsize="64"/>
> </feature>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6048541606..1755fd9d51 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -187,13 +187,17 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
>
> static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
> {
> - if (n == 0) {
> #ifdef CONFIG_USER_ONLY
> + if (n >= 0 && n <= 1) {
> return gdb_get_regl(buf, 0);
> + }
> #else
> + if (n == 0) {
> return gdb_get_regl(buf, cs->priv);
> -#endif
> + } else if (n == 1) {
> + return gdb_get_regl(buf, riscv_cpu_virt_enabled(cs));
> }
> +#endif
> return 0;
> }
>
> @@ -328,13 +332,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> case MXL_RV32:
> gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-32bit-virtual.xml", 0);
> + 2, "riscv-32bit-virtual.xml", 0);
> break;
> case MXL_RV64:
> case MXL_RV128:
> gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-64bit-virtual.xml", 0);
> + 2, "riscv-64bit-virtual.xml", 0);
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> break;
> default:
> g_assert_not_reached();
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
2023-03-05 9:42 [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads Jim Shu
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
2023-03-06 11:22 ` [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads LIU Zhiwei
@ 2023-03-10 0:05 ` Alistair Francis
2 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2023-03-10 0:05 UTC (permalink / raw)
To: Jim Shu
Cc: qemu-devel, qemu-riscv, Alex Bennée,
Philippe Mathieu-Daudé, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
On Sun, Mar 5, 2023 at 7:43 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch enables a debugger to read current virtualization mode via
> virtual "virt" register. After it, we could get full current privilege
> mode via both "priv" and "virt" register.
>
> Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
> support H-extension.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> gdb-xml/riscv-32bit-virtual.xml | 1 +
> gdb-xml/riscv-64bit-virtual.xml | 1 +
> target/riscv/gdbstub.c | 12 ++++++++----
> 3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml
> index 905f1c555d..d44b6ca2dc 100644
> --- a/gdb-xml/riscv-32bit-virtual.xml
> +++ b/gdb-xml/riscv-32bit-virtual.xml
> @@ -8,4 +8,5 @@
> <!DOCTYPE feature SYSTEM "gdb-target.dtd">
> <feature name="org.gnu.gdb.riscv.virtual">
> <reg name="priv" bitsize="32"/>
> + <reg name="virt" bitsize="32"/>
> </feature>
> diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml
> index 62d86c237b..7c9b63d5b6 100644
> --- a/gdb-xml/riscv-64bit-virtual.xml
> +++ b/gdb-xml/riscv-64bit-virtual.xml
> @@ -8,4 +8,5 @@
> <!DOCTYPE feature SYSTEM "gdb-target.dtd">
> <feature name="org.gnu.gdb.riscv.virtual">
> <reg name="priv" bitsize="64"/>
> + <reg name="virt" bitsize="64"/>
> </feature>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6048541606..1755fd9d51 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -187,13 +187,17 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
>
> static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
> {
> - if (n == 0) {
> #ifdef CONFIG_USER_ONLY
> + if (n >= 0 && n <= 1) {
> return gdb_get_regl(buf, 0);
> + }
> #else
> + if (n == 0) {
> return gdb_get_regl(buf, cs->priv);
> -#endif
> + } else if (n == 1) {
> + return gdb_get_regl(buf, riscv_cpu_virt_enabled(cs));
> }
> +#endif
> return 0;
> }
>
> @@ -328,13 +332,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> case MXL_RV32:
> gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-32bit-virtual.xml", 0);
> + 2, "riscv-32bit-virtual.xml", 0);
> break;
> case MXL_RV64:
> case MXL_RV128:
> gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-64bit-virtual.xml", 0);
> + 2, "riscv-64bit-virtual.xml", 0);
> break;
> default:
> g_assert_not_reached();
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-03-10 4:00 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-05 9:42 [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads Jim Shu
2023-03-05 9:42 ` [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB Jim Shu
2023-03-06 11:26 ` LIU Zhiwei
2023-03-08 11:14 ` Jim Shu
2023-03-09 3:05 ` Jim Shu
2023-03-09 3:21 ` LIU Zhiwei
2023-03-10 3:58 ` Alistair Francis
2023-03-06 11:22 ` [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads LIU Zhiwei
2023-03-10 0:05 ` Alistair Francis
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