From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Samuel Tardieu <sam@rfc1149.net>, qemu-devel@nongnu.org
Cc: "Anton Kochkov" <anton.kochkov@proton.me>,
qemu-arm@nongnu.org, "Alexandre Iooss" <erdnaxe@crans.org>,
"Arnaud Minier" <arnaud.minier@telecom-paris.fr>,
"Inès Varhol" <ines.varhol@telecom-paris.fr>,
"Alistair Francis" <alistair@alistair23.me>,
"Peter Maydell" <peter.maydell@linaro.org>
Subject: Re: [PATCH v3 2/3] hw/arm/armv7m: alias the NVIC "num-prio-bits" property
Date: Mon, 8 Jan 2024 13:03:05 +0100 [thread overview]
Message-ID: <0ba00ce5-0b4c-4e43-890d-9ebe6ecca6bc@linaro.org> (raw)
In-Reply-To: <20240106181503.1746200-3-sam@rfc1149.net>
On 6/1/24 19:15, Samuel Tardieu wrote:
> A SoC will not have a direct access to the NVIC embedded in its ARM
> core. By aliasing the "num-prio-bits" property similarly to what is
> done for the "num-irq" one, a SoC can easily configure it on its
> armv7m instance.
>
> Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/armv7m.c | 2 ++
> include/hw/arm/armv7m.h | 1 +
> 2 files changed, 3 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2024-01-08 12:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-06 18:15 [PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices Samuel Tardieu
2024-01-06 18:15 ` [PATCH v3 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property Samuel Tardieu
2024-01-06 18:15 ` [PATCH v3 2/3] hw/arm/armv7m: alias the NVIC " Samuel Tardieu
2024-01-08 12:03 ` Philippe Mathieu-Daudé [this message]
2024-01-06 18:15 ` [PATCH v3 3/3] hw/arm/socs: configure priority bits for existing SOCs Samuel Tardieu
2024-01-08 14:47 ` [PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices Peter Maydell
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