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Mon, 22 Apr 2024 08:24:11 -0700 (PDT) Message-ID: <0bab0cf5-0d74-48ff-9977-9f52471b717f@linaro.org> Date: Mon, 22 Apr 2024 08:24:08 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT From: Richard Henderson To: Peter Maydell Cc: Dorjoy Chowdhury , qemu-devel@nongnu.org References: <20240419183135.12276-1-dorjoychy111@gmail.com> <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org> Content-Language: en-US In-Reply-To: <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/22/24 08:21, Richard Henderson wrote: >>> For Arm's CPUs they fall into two categories: >>>   * older ones don't set MT in their MPIDR, and the Aff0 >>>     field is effectively the CPU number >>>   * newer ones do set MT in their MPIDR, but don't have >>>     SMT, so their Aff0 is always 0 and their Aff1 >>>     is the CPU number >>> >>> Of all the CPUs we model, none of them are the >>> architecturally-permitted "MT is set, CPU implements >>> actual SMT, Aff0 indicates the thread in the CPU" type. >> >> Looking at the TRM, Neoverse-E1 is "MT is set, actual SMT, >> Aff0 is the thread" (Aff0 can be 0 or 1). We just don't >> model that CPU type yet. But we should probably make >> sure we don't block ourselves into a corner where that >> would be awkward -- I'll have a think about this and >> look at what x86 does with the topology info. > > I'm suggesting that we set things up per -smp, and if the user chooses a -cpu value for > which that topology doesn't make sense, we do it anyway and let them keep both pieces. ... but more practically, it allows experimentation at -cpu max, without having to build in anything cpu-specific. Good to know about the E1 though... r~