From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com
Subject: Re: [Qemu-devel] [PATCH v1 1/1] tcg/riscv: Fix RISC-VH host build failure
Date: Tue, 25 Jun 2019 16:37:53 +0200 [thread overview]
Message-ID: <0bcb1b80-8a22-4e2f-b761-f9297ceff8ec@linaro.org> (raw)
In-Reply-To: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com>
On 6/20/19 4:04 PM, Alistair Francis wrote:
> Commit 269bd5d8 "cpu: Move the softmmu tlb to CPUNegativeOffsetState'
> broke the RISC-V host build as there are two variables that are used but
> not defined.
>
> This patch renames the undefined variables mask_off and table_off to the
> existing (but unused) mask_ofs and table_ofs variables.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Oops. Thanks, queued.
r~
prev parent reply other threads:[~2019-06-25 14:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 14:04 [Qemu-devel] [PATCH v1 1/1] tcg/riscv: Fix RISC-VH host build failure Alistair Francis
2019-06-25 14:37 ` Richard Henderson [this message]
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