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([2607:fb90:c9e1:9829:9eed:533c:6788:9f4a]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7be9ae8aaa9sm113008085a.34.2025.01.24.09.17.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jan 2025 09:17:20 -0800 (PST) Message-ID: <0bd61928-5bfc-44c7-8fc7-333f8e2e0b77@linaro.org> Date: Fri, 24 Jan 2025 09:17:17 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 20/28] target/riscv: Move has_work() from CPUClass to SysemuCPUOps To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini References: <20250121142341.17001-1-philmd@linaro.org> <20250121142341.17001-21-philmd@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250121142341.17001-21-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/21/25 06:23, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > target/riscv/cpu.h | 9 +++++---- > target/riscv/internals.h | 3 --- > target/riscv/cpu.c | 8 +++----- > 3 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 97713681cbe..32e8e064f36 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -552,10 +552,6 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); > uint8_t riscv_cpu_default_priority(int irq); > -uint64_t riscv_cpu_all_pending(CPURISCVState *env); > -int riscv_cpu_mirq_pending(CPURISCVState *env); > -int riscv_cpu_sirq_pending(CPURISCVState *env); > -int riscv_cpu_vsirq_pending(CPURISCVState *env); > bool riscv_cpu_fp_enabled(CPURISCVState *env); > target_ulong riscv_cpu_get_geilen(CPURISCVState *env); > void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); > @@ -576,6 +572,11 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc); > bool riscv_cpu_option_set(const char *optname); > > #ifndef CONFIG_USER_ONLY > +bool riscv_cpu_has_work(CPUState *cs); > +uint64_t riscv_cpu_all_pending(CPURISCVState *env); > +int riscv_cpu_mirq_pending(CPURISCVState *env); > +int riscv_cpu_sirq_pending(CPURISCVState *env); > +int riscv_cpu_vsirq_pending(CPURISCVState *env); > void riscv_cpu_do_interrupt(CPUState *cpu); > void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); > void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > diff --git a/target/riscv/internals.h b/target/riscv/internals.h > index 67291933f84..86def39aec2 100644 > --- a/target/riscv/internals.h > +++ b/target/riscv/internals.h > @@ -142,9 +142,6 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) > } > } > > -/* Our implementation of CPUClass::has_work */ > -bool riscv_cpu_has_work(CPUState *cs); > - Why move the declaration from internals.h to cpu.h? r~