From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Alistair Francis <alistair23@gmail.com>, qemu-devel@nongnu.org
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper
Date: Fri, 8 Sep 2023 15:21:29 +0200 [thread overview]
Message-ID: <0bdad3e3-bfd6-ffea-a725-46b9e4629756@linaro.org> (raw)
In-Reply-To: <20230908060431.1903919-49-alistair.francis@wdc.com>
On 8/9/23 08:04, Alistair Francis wrote:
> From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
> Future patches will split the existing Property arrays even further, and
> the existing code in riscv_cpu_add_user_properties() will start to scale
> bad with it because it's dealing with KVM constraints mixed in with TCG
> constraints. We're going to pay a high price to share a couple of common
> lines of code between the two.
>
> Create a new riscv_cpu_add_kvm_properties() that will be forked from
> riscv_cpu_add_user_properties() if we're running KVM. The helper
> includes all properties that a KVM CPU will add. The rest of
> riscv_cpu_add_user_properties() body will then be relieved from having
> to deal with KVM constraints.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Message-ID: <20230901194627.1214811-4-dbarboza@ventanamicro.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 42 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db640e7460..8e6d316500 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1943,6 +1943,46 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
> }
> #endif
>
> +#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_KVM ?
> +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> +{
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, prop_name)) {
> + return;
> + }
> +
> + /*
> + * Set the default to disabled for every extension
> + * unknown to KVM and error out if the user attempts
> + * to enable any of them.
> + */
> + object_property_add(obj, prop_name, "bool",
> + NULL, cpu_set_cfg_unavailable,
> + NULL, (void *)prop_name);
> +}
> +
> +static void riscv_cpu_add_kvm_properties(Object *obj)
> +{
> + Property *prop;
> + DeviceState *dev = DEVICE(obj);
> +
> + kvm_riscv_init_user_properties(obj);
> + riscv_cpu_add_misa_properties(obj);
> +
> + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> + riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> + }
> +
> + for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, riscv_cpu_options[i].name)) {
> + continue;
> + }
> + qdev_property_add_static(dev, &riscv_cpu_options[i]);
> + }
> +}
> +#endif
> +
> /*
> * Add CPU properties with user-facing flags.
> *
> @@ -1958,39 +1998,18 @@ static void riscv_cpu_add_user_properties(Object *obj)
> riscv_add_satp_mode_properties(obj);
>
> if (kvm_enabled()) {
> - kvm_riscv_init_user_properties(obj);
> + riscv_cpu_add_kvm_properties(obj);
> + return;
> }
> #endif
>
> riscv_cpu_add_misa_properties(obj);
>
> for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> -#ifndef CONFIG_USER_ONLY
> - if (kvm_enabled()) {
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, prop->name)) {
> - continue;
> - }
> -
> - /*
> - * Set the default to disabled for every extension
> - * unknown to KVM and error out if the user attempts
> - * to enable any of them.
> - */
> - object_property_add(obj, prop->name, "bool",
> - NULL, cpu_set_cfg_unavailable,
> - NULL, (void *)prop->name);
> - continue;
> - }
> -#endif
> qdev_property_add_static(dev, prop);
> }
>
> for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) {
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, riscv_cpu_options[i].name)) {
> - continue;
> - }
> qdev_property_add_static(dev, &riscv_cpu_options[i]);
> }
> }
next prev parent reply other threads:[~2023-09-08 13:22 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-08 6:03 [PULL 00/65] riscv-to-apply queue Alistair Francis
2023-09-08 6:03 ` [PULL 01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG Alistair Francis
2023-09-08 6:03 ` [PULL 02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts Alistair Francis
2023-09-08 6:03 ` [PULL 03/65] hw/char/riscv_htif: Fix the console syscall " Alistair Francis
2023-09-08 6:15 ` Michael Tokarev
2023-09-08 6:03 ` [PULL 04/65] target/riscv/cpu.c: add zmmul isa string Alistair Francis
2023-09-08 6:03 ` [PULL 05/65] target/riscv/cpu.c: add smepmp " Alistair Francis
2023-09-08 6:03 ` [PULL 06/65] target/riscv: Fix page_check_range use in fault-only-first Alistair Francis
2023-09-08 6:03 ` [PULL 07/65] target/riscv: Use existing lookup tables for MixColumns Alistair Francis
2023-09-08 6:03 ` [PULL 08/65] target/riscv: Refactor some of the generic vector functionality Alistair Francis
2023-09-08 6:03 ` [PULL 09/65] target/riscv: Refactor vector-vector translation macro Alistair Francis
2023-09-08 6:03 ` [PULL 10/65] target/riscv: Remove redundant "cpu_vl == 0" checks Alistair Francis
2023-09-08 6:03 ` [PULL 11/65] target/riscv: Add Zvbc ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 12/65] target/riscv: Move vector translation checks Alistair Francis
2023-09-08 6:03 ` [PULL 13/65] target/riscv: Refactor translation of vector-widening instruction Alistair Francis
2023-09-08 6:03 ` [PULL 14/65] target/riscv: Refactor some of the generic vector functionality Alistair Francis
2023-09-08 6:03 ` [PULL 15/65] target/riscv: Add Zvbb ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 16/65] target/riscv: Add Zvkned " Alistair Francis
2023-09-08 6:03 ` [PULL 17/65] target/riscv: Add Zvknh " Alistair Francis
2023-09-08 6:03 ` [PULL 18/65] target/riscv: Add Zvksh " Alistair Francis
2023-09-08 6:03 ` [PULL 19/65] target/riscv: Add Zvkg " Alistair Francis
2023-09-08 6:03 ` [PULL 20/65] crypto: Create sm4_subword Alistair Francis
2023-09-08 6:03 ` [PULL 21/65] crypto: Add SM4 constant parameter CK Alistair Francis
2023-09-08 6:03 ` [PULL 22/65] target/riscv: Add Zvksed ISA extension support Alistair Francis
2023-09-08 6:03 ` [PULL 23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren Alistair Francis
2023-09-08 6:03 ` [PULL 24/65] target/riscv: Add Zihintntl extension ISA string to DTS Alistair Francis
2023-09-08 6:03 ` [PULL 25/65] target/riscv: Fix zfa fleq.d and fltq.d Alistair Francis
2023-09-08 6:03 ` [PULL 26/65] hw/intc: Fix upper/lower mtime write calculation Alistair Francis
2023-09-08 6:03 ` [PULL 27/65] hw/intc: Make rtc variable names consistent Alistair Francis
2023-09-08 6:03 ` [PULL 28/65] linux-user/riscv: Use abi type for target_ucontext Alistair Francis
2023-09-08 6:03 ` [PULL 29/65] target/riscv: support the AIA device emulation with KVM enabled Alistair Francis
2023-09-08 6:03 ` [PULL 30/65] target/riscv: check the in-kernel irqchip support Alistair Francis
2023-09-08 6:03 ` [PULL 31/65] target/riscv: Create an KVM AIA irqchip Alistair Francis
2023-09-08 6:03 ` [PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA Alistair Francis
2023-09-08 6:03 ` [PULL 33/65] target/riscv: select KVM AIA in riscv virt machine Alistair Francis
2023-09-08 6:04 ` [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path Alistair Francis
2023-09-08 6:04 ` [PULL 35/65] target/riscv: Update CSR bits name for svadu extension Alistair Francis
2023-09-08 6:04 ` [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 Alistair Francis
2023-09-08 6:04 ` [PULL 37/65] riscv: zicond: make non-experimental Alistair Francis
2023-09-08 6:04 ` [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build Alistair Francis
2023-09-08 6:04 ` [PULL 39/65] hw/intc/riscv_aplic.c " Alistair Francis
2023-09-08 6:04 ` [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe Alistair Francis
2023-09-08 6:04 ` [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I Alistair Francis
2023-09-08 6:04 ` [PULL 42/65] target/riscv: Allocate itrigger timers only once Alistair Francis
2023-09-08 6:04 ` [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes Alistair Francis
2023-09-08 6:04 ` [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec Alistair Francis
2023-09-08 6:04 ` [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64 Alistair Francis
2023-09-08 6:04 ` [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Alistair Francis
2023-09-08 6:04 ` [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Alistair Francis
2023-09-08 6:04 ` [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper Alistair Francis
2023-09-08 13:21 ` Philippe Mathieu-Daudé [this message]
2023-09-10 8:58 ` Daniel Henrique Barboza
2023-09-11 2:15 ` Alistair Francis
2023-09-08 6:04 ` [PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] Alistair Francis
2023-09-08 6:04 ` [PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Alistair Francis
2023-09-08 6:04 ` [PULL 51/65] target/riscv/cpu.c: split vendor " Alistair Francis
2023-09-08 6:04 ` [PULL 52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() Alistair Francis
2023-09-08 6:04 ` [PULL 53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() Alistair Francis
2023-09-08 6:04 ` [PULL 54/65] target/riscv/cpu.c: limit cfg->vext_spec log message Alistair Francis
2023-09-08 6:04 ` [PULL 55/65] target/riscv: add 'max' CPU type Alistair Francis
2023-09-08 6:04 ` [PULL 56/65] avocado, risc-v: add tuxboot tests for 'max' CPU Alistair Francis
2023-09-08 6:04 ` [PULL 57/65] target/riscv: deprecate the 'any' CPU type Alistair Francis
2023-09-08 6:04 ` [PULL 58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Alistair Francis
2023-09-08 6:04 ` [PULL 59/65] target/riscv: make CPUCFG() macro public Alistair Francis
2023-09-08 6:04 ` [PULL 60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Alistair Francis
2023-09-08 6:04 ` [PULL 61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Alistair Francis
2023-09-08 6:04 ` [PULL 62/65] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Alistair Francis
2023-09-08 6:04 ` [PULL 63/65] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Alistair Francis
2023-09-08 6:04 ` [PULL 64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Alistair Francis
2023-09-08 6:04 ` [PULL 65/65] target/riscv/cpu.c: consider user option with RVG Alistair Francis
2023-09-08 6:38 ` [PULL 00/65] riscv-to-apply queue Michael Tokarev
2023-09-11 2:37 ` Alistair Francis
2023-09-08 11:06 ` Stefan Hajnoczi
2023-09-11 13:38 ` Daniel Henrique Barboza
2023-09-11 14:07 ` Stefan Hajnoczi
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