From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andrew Jeffery" <andrew@aj.id.au>,
"Joel Stanley" <joel@jms.id.au>,
"Alistair Francis" <alistair@alistair23.me>,
"Cleber Rosa" <crosa@redhat.com>,
"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
"Beraldo Leal" <bleal@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: steven_lee@aspeedtech.com, troy_lee@aspeedtech.com
Subject: Re: [PATCH v5 7/9] aspeed/soc : Add AST1030 support
Date: Thu, 29 Dec 2022 12:16:00 +0100 [thread overview]
Message-ID: <0c4810ae-edee-41df-7609-a3c6577a9ed3@linaro.org> (raw)
In-Reply-To: <20220401083850.15266-8-jamin_lin@aspeedtech.com>
Hi,
On 1/4/22 10:38, Jamin Lin wrote:
> From: Steven Lee <steven_lee@aspeedtech.com>
>
> The embedded core of AST1030 SoC is ARM Coretex M4.
> It is hard to be integrated in the common Aspeed Soc framework.
> We introduce a new ast1030 class with instance_init and realize
> handlers.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/arm/aspeed_ast10xx.c | 299 ++++++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 6 +-
> include/hw/arm/aspeed_soc.h | 3 +
> 3 files changed, 307 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/aspeed_ast10xx.c
> +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> +{
> + AspeedSoCState *s = ASPEED_SOC(dev_soc);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + MemoryRegion *system_memory = get_system_memory();
> + DeviceState *armv7m;
> + Error *err = NULL;
> + int i;
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /* General I/O memory space to catch all unimplemented device */
> + create_unimplemented_device("aspeed.sbc",
> + sc->memmap[ASPEED_DEV_SBC],
> + 0x40000);
> + create_unimplemented_device("aspeed.io",
> + sc->memmap[ASPEED_DEV_IOMEM],
> + ASPEED_SOC_IOMEM_SIZE);
> +
> + /* AST1030 CPU Core */
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 256);
Can you confirm this SoC has 256 and not 240 IRQs?
> + qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + object_property_set_link(OBJECT(&s->armv7m), "memory",
> + OBJECT(system_memory), &error_abort);
> + sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
next prev parent reply other threads:[~2022-12-29 11:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-01 8:38 [PATCH v5 0/9] Add support for AST1030 SoC Jamin Lin
2022-04-01 8:38 ` [PATCH v5 1/9] aspeed/adc: Add AST1030 support Jamin Lin
2022-04-01 8:38 ` [PATCH v5 2/9] aspeed/smc: " Jamin Lin
2022-04-01 8:38 ` [PATCH v5 3/9] aspeed/wdt: Fix ast2500/ast2600 default reload value Jamin Lin
2022-04-01 8:38 ` [PATCH v5 4/9] aspeed/wdt: Add AST1030 support Jamin Lin
2022-04-01 8:38 ` [PATCH v5 5/9] aspeed/timer: " Jamin Lin
2022-04-01 8:38 ` [PATCH v5 6/9] aspeed/scu: " Jamin Lin
2022-04-01 8:38 ` [PATCH v5 7/9] aspeed/soc : " Jamin Lin
2022-12-29 11:16 ` Philippe Mathieu-Daudé [this message]
2023-02-23 10:44 ` Philippe Mathieu-Daudé
2023-02-24 4:06 ` Troy Lee
2022-04-01 8:38 ` [PATCH v5 8/9] aspeed: Add an AST1030 eval board Jamin Lin
2022-04-01 8:47 ` Cédric Le Goater
2022-04-01 8:38 ` [PATCH v5 9/9] test/avocado/machine_aspeed.py: Add ast1030 test case Jamin Lin
2022-04-01 8:55 ` [PATCH v5 0/9] Add support for AST1030 SoC Cédric Le Goater
2022-04-01 9:23 ` Jamin Lin
2022-04-01 9:47 ` Jamin Lin
2022-04-01 13:13 ` Cédric Le Goater
2022-04-01 13:25 ` Cédric Le Goater
2022-04-11 1:49 ` Jamin Lin
2022-04-05 16:12 ` Cédric Le Goater
2022-04-11 2:07 ` Jamin Lin
2022-04-11 8:23 ` Cédric Le Goater
2022-04-11 8:58 ` Jamin Lin
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