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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9a89c2sm1540149b3a.94.2024.11.14.10.09.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2024 10:09:56 -0800 (PST) Message-ID: <0cd1e8cc-4c99-496f-9830-ac96e03f5241@linaro.org> Date: Thu, 14 Nov 2024 10:09:55 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 23/54] accel/tcg: Check original prot bits for read in atomic_mmu_lookup Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241114160131.48616-1-richard.henderson@linaro.org> <20241114160131.48616-24-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241114160131.48616-24-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/14/24 08:00, Richard Henderson wrote: > In the mist before CPUTLBEntryFull existed, we had to be > clever to detect write-only pages. Now we can directly > test the saved prot bits, which is clearer. > > Signed-off-by: Richard Henderson > --- > accel/tcg/cputlb.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index c975dd2322..ae3a99eb47 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -1854,14 +1854,13 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, > flags &= ~TLB_INVALID_MASK; > } > } > + full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; > > /* > * Let the guest notice RMW on a write-only page. > * We have just verified that the page is writable. > - * Subpage lookups may have left TLB_INVALID_MASK set, > - * but addr_read will only be -1 if PAGE_READ was unset. > */ > - if (unlikely(tlbe->addr_read == -1)) { > + if (unlikely(!(full->prot & PAGE_READ))) { > tlb_fill_align(cpu, addr, MMU_DATA_LOAD, mmu_idx, > 0, size, false, retaddr); > /* > @@ -1899,7 +1898,6 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, > } > > hostaddr = (void *)((uintptr_t)addr + tlbe->addend); > - full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; > > if (unlikely(flags & TLB_NOTDIRTY)) { > notdirty_write(cpu, addr, size, full, retaddr); Reviewed-by: Pierrick Bouvier