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Tue, 15 Apr 2025 14:05:18 -0700 (PDT) Received: from [192.168.1.87] ([38.39.164.180]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-308613661efsm38890a91.46.2025.04.15.14.05.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 14:05:18 -0700 (PDT) Message-ID: <0cee7116-6c16-4026-b2bb-f5bcc76529c4@linaro.org> Date: Tue, 15 Apr 2025 14:05:17 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-47-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-47-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:23, Richard Henderson wrote: > Rename to INDEX_op_divs2 to emphasize signed inputs, > and mirroring INDEX_op_divu2_*. Document the opcode. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-opc.h | 3 +-- > tcg/tcg-op.c | 16 ++++++++-------- > tcg/tcg.c | 6 ++---- > docs/devel/tcg-ops.rst | 9 +++++++++ > 4 files changed, 20 insertions(+), 14 deletions(-) > > diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h > index 243f002a61..36dfbf80ad 100644 > --- a/include/tcg/tcg-opc.h > +++ b/include/tcg/tcg-opc.h > @@ -43,6 +43,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT) > DEF(and, 1, 2, 0, TCG_OPF_INT) > DEF(andc, 1, 2, 0, TCG_OPF_INT) > DEF(divs, 1, 2, 0, TCG_OPF_INT) > +DEF(divs2, 2, 3, 0, TCG_OPF_INT) > DEF(divu, 1, 2, 0, TCG_OPF_INT) > DEF(eqv, 1, 2, 0, TCG_OPF_INT) > DEF(mul, 1, 2, 0, TCG_OPF_INT) > @@ -72,7 +73,6 @@ DEF(st_i32, 0, 2, 1, 0) > /* arith */ > DEF(rem_i32, 1, 2, 0, 0) > DEF(remu_i32, 1, 2, 0, 0) > -DEF(div2_i32, 2, 3, 0, 0) > DEF(divu2_i32, 2, 3, 0, 0) > /* shifts/rotates */ > DEF(shl_i32, 1, 2, 0, 0) > @@ -118,7 +118,6 @@ DEF(st_i64, 0, 2, 1, 0) > /* arith */ > DEF(rem_i64, 1, 2, 0, 0) > DEF(remu_i64, 1, 2, 0, 0) > -DEF(div2_i64, 2, 3, 0, 0) > DEF(divu2_i64, 2, 3, 0, 0) > /* shifts/rotates */ > DEF(shl_i64, 1, 2, 0, 0) > diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c > index f326c452a4..f95beb8b5d 100644 > --- a/tcg/tcg-op.c > +++ b/tcg/tcg-op.c > @@ -603,10 +603,10 @@ void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) > { > if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { > tcg_gen_op3_i32(INDEX_op_divs, ret, arg1, arg2); > - } else if (TCG_TARGET_HAS_div2_i32) { > + } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { > TCGv_i32 t0 = tcg_temp_ebb_new_i32(); > tcg_gen_sari_i32(t0, arg1, 31); > - tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); > + tcg_gen_op5_i32(INDEX_op_divs2, ret, t0, arg1, t0, arg2); > tcg_temp_free_i32(t0); > } else { > gen_helper_div_i32(ret, arg1, arg2); > @@ -623,10 +623,10 @@ void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) > tcg_gen_mul_i32(t0, t0, arg2); > tcg_gen_sub_i32(ret, arg1, t0); > tcg_temp_free_i32(t0); > - } else if (TCG_TARGET_HAS_div2_i32) { > + } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { > TCGv_i32 t0 = tcg_temp_ebb_new_i32(); > tcg_gen_sari_i32(t0, arg1, 31); > - tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); > + tcg_gen_op5_i32(INDEX_op_divs2, t0, ret, arg1, t0, arg2); > tcg_temp_free_i32(t0); > } else { > gen_helper_rem_i32(ret, arg1, arg2); > @@ -1971,10 +1971,10 @@ void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) > { > if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) { > tcg_gen_op3_i64(INDEX_op_divs, ret, arg1, arg2); > - } else if (TCG_TARGET_HAS_div2_i64) { > + } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) { > TCGv_i64 t0 = tcg_temp_ebb_new_i64(); > tcg_gen_sari_i64(t0, arg1, 63); > - tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); > + tcg_gen_op5_i64(INDEX_op_divs2, ret, t0, arg1, t0, arg2); > tcg_temp_free_i64(t0); > } else { > gen_helper_div_i64(ret, arg1, arg2); > @@ -1991,10 +1991,10 @@ void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) > tcg_gen_mul_i64(t0, t0, arg2); > tcg_gen_sub_i64(ret, arg1, t0); > tcg_temp_free_i64(t0); > - } else if (TCG_TARGET_HAS_div2_i64) { > + } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) { > TCGv_i64 t0 = tcg_temp_ebb_new_i64(); > tcg_gen_sari_i64(t0, arg1, 63); > - tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); > + tcg_gen_op5_i64(INDEX_op_divs2, t0, ret, arg1, t0, arg2); > tcg_temp_free_i64(t0); > } else { > gen_helper_rem_i64(ret, arg1, arg2); > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 563a29e579..f6192142ba 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1028,8 +1028,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = { > OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), > OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), > OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), > - OUTOP(INDEX_op_div2_i32, TCGOutOpDivRem, outop_divs2), > - OUTOP(INDEX_op_div2_i64, TCGOutOpDivRem, outop_divs2), > + OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), > OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), > OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), > OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh), > @@ -5470,8 +5469,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) > } > break; > > - case INDEX_op_div2_i32: > - case INDEX_op_div2_i64: > + case INDEX_op_divs2: > { > const TCGOutOpDivRem *out = > container_of(all_outop[op->opc], TCGOutOpDivRem, base); > diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst > index 41985be012..62af390854 100644 > --- a/docs/devel/tcg-ops.rst > +++ b/docs/devel/tcg-ops.rst > @@ -297,6 +297,15 @@ Arithmetic > - | *t0* = *t1* % *t2* (unsigned) > | Undefined behavior if division by zero. > > + * - divs2 *q*, *r*, *nl*, *nh*, *d* > + > + - | *q* = *nh:nl* / *d* (signed) > + | *r* = *nh:nl* % *d* > + | Undefined behaviour if division by zero, or the double-word > + numerator divided by the single-word divisor does not fit > + within the single-word quotient. The code generator will > + pass *nh* as a simple sign-extension of *nl*, so the only > + overflow should be *INT_MIN* / -1. > > Logical > ------- Reviewed-by: Pierrick Bouvier