From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: qemu-devel@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Anton Johansson" <anjo@rev.ng>,
"Jason Wang" <jasowang@redhat.com>,
qemu-arm@nongnu.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Gustavo Romero" <gustavo.romero@linaro.org>
Subject: Re: [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls
Date: Thu, 14 Nov 2024 19:55:11 +0100 [thread overview]
Message-ID: <0cf1cdc6-442f-45f8-b1e7-346b236b516a@linaro.org> (raw)
In-Reply-To: <ZzTHj3uHGfc2Z8Dd@zapote>
On 13/11/24 15:36, Edgar E. Iglesias wrote:
> On Tue, Nov 12, 2024 at 07:10:24PM +0100, Philippe Mathieu-Daudé wrote:
>> This is the result of a long discussion with Edgar (started few
>> years ago!) and Paolo:
>> https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/
>> After clarification from Richard on MMIO/RAM accesses, I figured
>> strengthening the model regions would make things obvious,
>> eventually allowing to remove the tswap() calls for good.
>>
>> This costly series mostly plays around with MemoryRegions.
>>
>> The model has a mix of RAM/MMIO in its address range. Currently
>> they are implemented as a MMIO array of u32. Since the core
>> memory layer swaps accesses for MMIO, the device implementation
>> has to swap them back.
>> In order to avoid that, we'll map the RAM regions as RAM MRs.
>> First we move each MMIO register to new MMIO regions (RX and TX).
>> Then what is left are the RAM buffers; we convert them to RAM MRs,
>> removing the need for tswap() at all.
>>
>> Once reviewed, I'll respin my "hw/microblaze: Allow running
>> cross-endian vCPUs" series based on this.
>
>
> Thanks Phil,
>
> This looks good to me. Have you tested this with the Images I provied
> a while back or some other way?
I'm running the same functional tests run on CI:
$ make check-functional-microblaze{,el}
[1/7] Generating qemu-version.h with a custom command (wrapped by meson
to capture output)
[1/7] Generating qemu-version.h with a custom command (wrapped by meson
to capture output)
/Users/philmd/qemu/build/pyvenv/bin/meson test --no-rebuild -t 1
--setup thorough --print-errorlogs --suite func-microblazeel --suite
func-microblazeel-thorough
/Users/philmd/qemu/build/pyvenv/bin/meson test --no-rebuild -t 1
--setup thorough --print-errorlogs --suite func-microblaze --suite
func-microblaze-thorough
1/4 qemu:func-quick+func-microblazeel /
func-microblazeel-empty_cpu_model OK
0.18s 1 subtests passed
1/4 qemu:func-quick+func-microblaze / func-microblaze-empty_cpu_model
OK 0.18s 1 subtests passed
2/4 qemu:func-quick+func-microblaze / func-microblaze-version
OK 0.18s 1 subtests passed
2/4 qemu:func-quick+func-microblazeel / func-microblazeel-version
OK 0.18s 1 subtests
passed
3/4 qemu:func-quick+func-microblaze / func-microblaze-info_usernet
OK 0.28s 1 subtests passed
3/4 qemu:func-quick+func-microblazeel / func-microblazeel-info_usernet
OK 0.28s 1 subtests
passed
4/4 qemu:func-thorough+func-microblaze-thorough+thorough /
func-microblaze-microblaze_s3adsp1800 OK 0.57s 1
subtests passed
Ok: 4
Expected Fail: 0
Fail: 0
Unexpected Pass: 0
Skipped: 0
Timeout: 0
Full log written to /Users/philmd/qemu/build/meson-logs/testlog-thorough.txt
4/4 qemu:func-thorough+func-microblazeel-thorough+thorough /
func-microblazeel-microblazeel_s3adsp1800 OK 1.50s
1 subtests passed
Ok: 4
Expected Fail: 0
Fail: 0
Unexpected Pass: 0
Skipped: 0
Timeout: 0
Full log written to /Users/philmd/qemu/build/meson-logs/testlog-thorough.txt
$
prev parent reply other threads:[~2024-11-14 18:58 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 18:10 [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 02/20] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 03/20] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-13 15:12 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size Philippe Mathieu-Daudé
2024-11-13 15:15 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Philippe Mathieu-Daudé
2024-11-13 15:16 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 07/20] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-13 15:20 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper Philippe Mathieu-Daudé
2024-11-13 15:23 ` Edgar E. Iglesias
2024-11-14 19:04 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 09/20] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 10/20] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 11/20] hw/net/xilinx_ethlite: Access RX_CTRL register for each port Philippe Mathieu-Daudé
2024-11-13 15:27 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 13/20] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 14/20] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 15/20] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-13 15:29 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:30 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 17/20] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 19/20] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 18:21 ` Paolo Bonzini
2024-11-13 19:37 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 20/20] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 15:36 ` [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Edgar E. Iglesias
2024-11-14 18:55 ` Philippe Mathieu-Daudé [this message]
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