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[83.52.173.228]) by smtp.gmail.com with ESMTPSA id k17sm15291292wrm.73.2019.05.20.10.20.39 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Mon, 20 May 2019 10:20:39 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190520162809.2677-1-peter.maydell@linaro.org> <20190520162809.2677-5-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <0d39932f-8959-cb68-1ac7-ac79cfdb98a9@redhat.com> Date: Mon, 20 May 2019 19:20:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190520162809.2677-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: Re: [Qemu-devel] [PATCH 4/4] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Peter, On 5/20/19 6:28 PM, Peter Maydell wrote: > The ICC_CTLR_EL3 register includes some bits which are aliases > of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses > to keep those bits in the cs->icc_ctlr_el1[] struct fields. > Unfortunately a missing '~' in the code to update the bits > in those fields meant that writing to ICC_CTLR_EL3 would corrupt > the ICC_CLTR_EL1 register values. How did you notice? Simply reviewing? > > Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > --- > hw/intc/arm_gicv3_cpuif.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c > index 000bdbd6247..3b212d91c8f 100644 > --- a/hw/intc/arm_gicv3_cpuif.c > +++ b/hw/intc/arm_gicv3_cpuif.c > @@ -1856,7 +1856,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, > trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); > > /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ > - cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); > + cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); > if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { > cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; > } > @@ -1864,7 +1864,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, > cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; > } > > - cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); > + cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); > if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { > cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; > } >