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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cadb2250d8sm1625696a34.13.2025.12.11.07.04.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Dec 2025 07:04:43 -0800 (PST) Message-ID: <0d3b4338-2c31-4e42-8a8e-319f3ad4029f@linaro.org> Date: Thu, 11 Dec 2025 09:04:40 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Record AS in full tlb To: Mark Burton , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Matheus Bernardino , Sid Manning , Brian Cain Cc: QEMU Developers References: From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -269,6 +269,8 @@ struct CPUTLBEntryFull { > bool guarded; > } arm; > } extra; > + > + AddressSpace *as; > }; ... > -MemoryRegionSection *iotlb_to_section(CPUState *cpu, > + > +MemoryRegionSection *iotlb_to_section(AddressSpace *as, > hwaddr index, MemTxAttrs attrs) > { > - int asidx = cpu_asidx_from_attrs(cpu, attrs); > - CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; > - AddressSpaceDispatch *d = address_space_to_dispatch(cpuas->as); > + assert(as); > + AddressSpaceDispatch *d = address_space_to_dispatch(as); > int section_index = index & ~TARGET_PAGE_MASK; Adding the as to CPUTLBEntryFull is unnecessary because (1) Each CPUTLB, and thus each CPUTLBEntryFull, is private to the cpu. (2) Each CPUTLBEntryFull contains the MemTxAttrs for the access. Thus the AddressSpace is purely a function of (cpu, attrs). We can have a conversation about where this lookup happens, and whether or not particular functions should be passed a CPUState, but adding AddressSpace to full tlb is redundant. r~