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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2db04966bcbsm8749076a91.41.2024.09.11.11.41.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Sep 2024 11:41:15 -0700 (PDT) Message-ID: <0d591570-02c6-48c9-9e3f-ef47ac20ce7d@linaro.org> Date: Wed, 11 Sep 2024 11:41:13 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, Swung0x48 , TANG Tiancheng References: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> <20240911132630.461-3-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240911132630.461-3-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/11/24 06:26, LIU Zhiwei wrote: > From: Swung0x48 > > The RISC-V vector instruction set utilizes the LMUL field to group > multiple registers, enabling variable-length vector registers. This > implementation uses only the first register number of each group while > reserving the other register numbers within the group. > > In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the > host runtime needs to adjust LMUL based on the type to use different > register groups. > > This presents challenges for TCG's register allocation. Currently, we > avoid modifying the register allocation part of TCG and only expose the > minimum number of vector registers. > > For example, when the host vlen is 64 bits and type is TCG_TYPE_V256, with > LMUL equal to 4, we use 4 vector registers as one register group. We can > use a maximum of 8 register groups, but the V0 register number is reserved > as a mask register, so we can effectively use at most 7 register groups. > Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers are > forced to be used. This is because TCG cannot yet dynamically constrain > registers with type; likewise, when the host vlen is 128 bits and > TCG_TYPE_V256, we can use at most 15 registers. > > There is not much pressure on vector register allocation in TCG now, so > using 7 registers is feasible and will not have a major impact on code > generation. > > This patch: > 1. Reserves vector register 0 for use as a mask register. > 2. When using register groups, reserves the additional registers within > each group. > > Signed-off-by: TANG Tiancheng > Co-authored-by: TANG Tiancheng If there is a co-author, there should be another Signed-off-by. > Reviewed-by: Liu Zhiwei > --- > tcg/riscv/tcg-target-con-str.h | 1 + > tcg/riscv/tcg-target.c.inc | 126 ++++++++++++++++++++++++--------- > tcg/riscv/tcg-target.h | 78 +++++++++++--------- > tcg/riscv/tcg-target.opc.h | 12 ++++ > 4 files changed, 151 insertions(+), 66 deletions(-) > create mode 100644 tcg/riscv/tcg-target.opc.h Anyway, Reviewed-by: Richard Henderson r~