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Tue, 28 May 2024 08:48:24 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1783158063; Tue, 28 May 2024 08:48:22 +0000 (GMT) Received: from [9.109.242.165] (unknown [9.109.242.165]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 28 May 2024 08:48:21 +0000 (GMT) Message-ID: <0d8011f6-653f-49fb-9cd8-008fc0029d78@linux.ibm.com> Date: Tue, 28 May 2024 14:18:20 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: Caleb Schlossin , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Daniel Henrique Barboza , qemu-devel@nongnu.org References: <20240526122612.473476-1-npiggin@gmail.com> <20240526122612.473476-7-npiggin@gmail.com> Content-Language: en-US From: Harsh Prateek Bora In-Reply-To: <20240526122612.473476-7-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zoKkVeO6kgGv228p6Qiz9Ocac_Sa0LCB X-Proofpoint-ORIG-GUID: O3y0mkwmVyjLx0LhVY-qGen1hTofO-yW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_05,2024-05-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 spamscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405280064 Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/26/24 17:56, Nicholas Piggin wrote: > The way SMT thread siblings are matched is clunky, using hard-coded > logic that checks the PIR SPR. > > Change that to use a new core_index variable in the CPUPPCState, > where all siblings have the same core_index. CPU realize routines have > flexibility in setting core/sibling topology. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h | 5 ++++- > hw/ppc/pnv_core.c | 2 ++ > hw/ppc/spapr_cpu_core.c | 3 +++ > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index dac13d4dac..9a89083932 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1247,6 +1247,9 @@ struct CPUArchState { > /* when a memory exception occurs, the access type is stored here */ > int access_type; > > + /* For SMT processors */ > + int core_index; > + > #if !defined(CONFIG_USER_ONLY) > /* MMU context, only relevant for full system emulation */ > #if defined(TARGET_PPC64) > @@ -1404,7 +1407,7 @@ struct CPUArchState { > }; > > #define _CORE_ID(cs) \ > - (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1)) > + (POWERPC_CPU(cs)->env.core_index) Dont we want to keep the logical & with ~(cs->nr_threads - 1) ? How's it taken care ? > > #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ > CPU_FOREACH(cs_sibling) \ > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 9b5edd9e48..0f61aabb77 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -252,6 +252,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, > pir_spr->default_value = pir; > tir_spr->default_value = tir; > > + env->core_index = core_hwid; > + > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); > } > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index e7c9edd033..059d372c8a 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -300,16 +300,19 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) > g_autofree char *id = NULL; > CPUState *cs; > PowerPCCPU *cpu; > + CPUPPCState *env; > > obj = object_new(scc->cpu_type); > > cs = CPU(obj); > cpu = POWERPC_CPU(obj); > + env = &cpu->env; > /* > * All CPUs start halted. CPU0 is unhalted from the machine level reset code > * and the rest are explicitly started up by the guest using an RTAS call. > */ > qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); > + env->core_index = cc->core_id; We could just do cpu->env.core_index and avoid creating local var env. regards, Harsh > cs->cpu_index = cc->core_id + i; > if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { > return NULL;