Re: [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi Alistair,

On 24/7/24 04:44, Alistair Francis wrote:
> On Sat, Jul 20, 2024 at 9:15 AM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>>
>> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
>> qemu-system-riscv64 can directly boot a RV32 Linux.
>>
>> This patch set has been tested with 6.9.0 Linux Image.
>> And add an avocado tuxrun test in tests/avocado.
>>
>> v6:
>>    Use TUXRUN test case instead of boot_linux_console
>>    Add any32 and max32 cpu for RV64 QEMU
>>
>> v5:
>>    Rebase to master and add tags
>>
>> v4:
>>    Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
>>    Avocado: Add "if=none" to "-drive" option in QEMU command line
>>
>> v3:
>>    Rebase to the master branch
>>
>> v2:
>>    Remove the line that was inadvertently left in PATCH v1 4/6.
>>    Add an avocado test.
>>
>> v1:
>>    https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>>
>>
>> LIU Zhiwei (2):
>>    target/riscv: Add any32 and max32 CPU for RV64 QEMU
>>    tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
>>
>> TANG Tiancheng (6):
>>    target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
>>    target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
>>    target/riscv: Correct SXL return value for RV32 in RV64 QEMU
>>    target/riscv: Detect sxl to set bit width for RV32 in RV64
>>    target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
>>    target/riscv: Enable RV32 CPU support in RV64 QEMU
> 
> Thanks!
> 
> Applied to riscv-to-apply.next

Please don't add the 'any32' CPU type, we are removing 'any':
https://lore.kernel.org/qemu-devel/20240724130717.95629-1-philmd@linaro.org/