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[92.88.170.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4280573f447sm19542095e9.16.2024.07.25.00.01.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jul 2024 00:01:37 -0700 (PDT) Message-ID: <0d864b83-be52-479f-bd4a-5019425e98b4@linaro.org> Date: Thu, 25 Jul 2024 09:01:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU To: Alistair Francis , LIU Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, alex.bennee@linaro.org References: <20240719231149.1364-1-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Alistair, On 24/7/24 04:44, Alistair Francis wrote: > On Sat, Jul 20, 2024 at 9:15 AM LIU Zhiwei wrote: >> >> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus >> qemu-system-riscv64 can directly boot a RV32 Linux. >> >> This patch set has been tested with 6.9.0 Linux Image. >> And add an avocado tuxrun test in tests/avocado. >> >> v6: >> Use TUXRUN test case instead of boot_linux_console >> Add any32 and max32 cpu for RV64 QEMU >> >> v5: >> Rebase to master and add tags >> >> v4: >> Drop UL completely in PATCH v3 2/7, 4/7, 5/7. >> Avocado: Add "if=none" to "-drive" option in QEMU command line >> >> v3: >> Rebase to the master branch >> >> v2: >> Remove the line that was inadvertently left in PATCH v1 4/6. >> Add an avocado test. >> >> v1: >> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html >> >> >> LIU Zhiwei (2): >> target/riscv: Add any32 and max32 CPU for RV64 QEMU >> tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU >> >> TANG Tiancheng (6): >> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI >> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 >> target/riscv: Correct SXL return value for RV32 in RV64 QEMU >> target/riscv: Detect sxl to set bit width for RV32 in RV64 >> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU >> target/riscv: Enable RV32 CPU support in RV64 QEMU > > Thanks! > > Applied to riscv-to-apply.next Please don't add the 'any32' CPU type, we are removing 'any': https://lore.kernel.org/qemu-devel/20240724130717.95629-1-philmd@linaro.org/