Re: [PATCH 1/3] target/ppc: Move VMX storage access instructions to decodetree

[Richard Henderson <richard.henderson@linaro.org>]

On 4/28/24 22:13, Chinmay Rath wrote:
> +static bool trans_LVX(DisasContext *ctx, arg_X *a)
> +{
> +    TCGv EA;
> +    TCGv_i64 avr;
> +    REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
> +    REQUIRE_VECTOR(ctx);
> +    gen_set_access_type(ctx, ACCESS_INT);
> +    avr = tcg_temp_new_i64();
> +    EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
> +    tcg_gen_andi_tl(EA, EA, ~0xf);
> +    /*
> +     * We only need to swap high and low halves. gen_qemu_ld64_i64
> +     * does necessary 64-bit byteswap already.
> +     */
> +    gen_qemu_ld64_i64(ctx, avr, EA);
> +    set_avr64(a->rt, avr, !ctx->le_mode);
> +    tcg_gen_addi_tl(EA, EA, 8);
> +    gen_qemu_ld64_i64(ctx, avr, EA);
> +    set_avr64(a->rt, avr, ctx->le_mode);
> +    return true;
> +}

This is an accurate transcription of the current code, so,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

but at some point this should use tcg_gen_qemu_ld_i128, with the proper atomicity flags.


r~