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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id g21-20020a056a000b9500b006e6b2ba1577sm19106885pfj.138.2024.04.29.05.48.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Apr 2024 05:48:11 -0700 (PDT) Message-ID: <0e33df55-9feb-403f-be87-952efdbaccd5@linaro.org> Date: Mon, 29 Apr 2024 05:48:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] target/ppc: Move VMX storage access instructions to decodetree To: Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, npiggin@gmail.com, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240429051317.289426-1-rathc@linux.ibm.com> <20240429051317.289426-2-rathc@linux.ibm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240429051317.289426-2-rathc@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/28/24 22:13, Chinmay Rath wrote: > +static bool trans_LVX(DisasContext *ctx, arg_X *a) > +{ > + TCGv EA; > + TCGv_i64 avr; > + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); > + REQUIRE_VECTOR(ctx); > + gen_set_access_type(ctx, ACCESS_INT); > + avr = tcg_temp_new_i64(); > + EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); > + tcg_gen_andi_tl(EA, EA, ~0xf); > + /* > + * We only need to swap high and low halves. gen_qemu_ld64_i64 > + * does necessary 64-bit byteswap already. > + */ > + gen_qemu_ld64_i64(ctx, avr, EA); > + set_avr64(a->rt, avr, !ctx->le_mode); > + tcg_gen_addi_tl(EA, EA, 8); > + gen_qemu_ld64_i64(ctx, avr, EA); > + set_avr64(a->rt, avr, ctx->le_mode); > + return true; > +} This is an accurate transcription of the current code, so, Reviewed-by: Richard Henderson but at some point this should use tcg_gen_qemu_ld_i128, with the proper atomicity flags. r~