[PATCH v3 0/3] Fix some loongarch tcg bugs

[PATCH v3 0/3] Fix some loongarch tcg bugs

[Song Gao]

Hi,

This series fix some bugs find from RISU test.

V3:
  -drop patch set some instruction result high 32bit 1.
  -follow some change from Richard's suggestion.

v2:
  -remove patch5 div if x/0 set dividend to 0.


Song Gao (3):
  target/loongarch: bstrins.w src register need EXT_NONE
  target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
  softfloat: logB(0) should raise divideByZero exception

 fpu/softfloat-parts.c.inc                     |  1 +
 target/loongarch/insn_trans/trans_bit.c.inc   | 36 +++++++++++--------
 .../loongarch/insn_trans/trans_farith.c.inc   | 12 +++----
 3 files changed, 29 insertions(+), 20 deletions(-)

-- 
2.31.1

[PATCH v3 1/3] target/loongarch: bstrins.w src register need EXT_NONE

[Song Gao]

use gen_bstrins/gen_bstrpic to replace gen_rr_ms_ls.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_bit.c.inc | 36 +++++++++++++--------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 9337714ec4..b01e4aeb23 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -27,26 +27,34 @@ static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
     tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
 }
 
-static void gen_bstrins(TCGv dest, TCGv src1,
-                        unsigned int ls, unsigned int len)
+static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
+                        DisasExtend dst_ext)
 {
-    tcg_gen_deposit_tl(dest, dest, src1, ls, len);
+    TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
+    TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
+    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+
+    if (a->ls > a->ms) {
+        return false;
+    }
+
+    tcg_gen_deposit_tl(dest, src1, src2, a->ls, a->ms - a->ls + 1);
+    gen_set_gpr(a->rd, dest, dst_ext);
+    return true;
 }
 
-static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
-                         DisasExtend src_ext, DisasExtend dst_ext,
-                         void (*func)(TCGv, TCGv, unsigned int, unsigned int))
+static bool gen_bstrpick(DisasContext *ctx, arg_rr_ms_ls *a,
+                         DisasExtend dst_ext)
 {
-    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
-    TCGv src1 = gpr_src(ctx, a->rj, src_ext);
+    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
 
     if (a->ls > a->ms) {
         return false;
     }
 
-    func(dest, src1, a->ls, a->ms - a->ls + 1);
+    tcg_gen_extract_tl(dest, src1, a->ls, a->ms - a->ls + 1);
     gen_set_gpr(a->rd, dest, dst_ext);
-
     return true;
 }
 
@@ -206,7 +214,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
 TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
 TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
 TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
-TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
-TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
-TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
+TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
+TRANS(bstrins_d, gen_bstrins, EXT_NONE)
+TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
+TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)
-- 
2.31.1

Re: [PATCH v3 1/3] target/loongarch: bstrins.w src register need EXT_NONE

[Richard Henderson]

On 9/29/22 19:45, Song Gao wrote:
> use gen_bstrins/gen_bstrpic to replace gen_rr_ms_ls.
> 
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
>   target/loongarch/insn_trans/trans_bit.c.inc | 36 +++++++++++++--------
>   1 file changed, 22 insertions(+), 14 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 2/3] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags

[Song Gao]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
index 65ad2ffab8..7bb3f41aee 100644
--- a/target/loongarch/insn_trans/trans_farith.c.inc
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
@@ -97,9 +97,9 @@ TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
 TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
 TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
 TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
-TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,
-      float_muladd_negate_product | float_muladd_negate_c)
-TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,
-      float_muladd_negate_product | float_muladd_negate_c)
-TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)
-TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)
+TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
+TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
+TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
+      float_muladd_negate_c | float_muladd_negate_result)
+TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
+      float_muladd_negate_c | float_muladd_negate_result)
-- 
2.31.1

[PATCH v3 3/3] softfloat: logB(0) should raise divideByZero exception

[Song Gao]

logB(0) should raise divideByZero exception from IEEE 754-2008 spec 7.3

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 fpu/softfloat-parts.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index a9f268fcab..247400031c 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -1436,6 +1436,7 @@ static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)
             parts_return_nan(a, s);
             return;
         case float_class_zero:
+            float_raise(float_flag_divbyzero, s);
             /* log2(0) = -inf */
             a->cls = float_class_inf;
             a->sign = 1;
-- 
2.31.1

Re: [PATCH v3 3/3] softfloat: logB(0) should raise divideByZero exception

[Richard Henderson]

On 9/29/22 19:45, Song Gao wrote:
> logB(0) should raise divideByZero exception from IEEE 754-2008 spec 7.3
> 
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
>   fpu/softfloat-parts.c.inc | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 0/3] Fix some loongarch tcg bugs

[gaosong]

在 2022/9/30 10:45, Song Gao 写道:
> Hi,
>
> This series fix some bugs find from RISU test.
>
> V3:
>    -drop patch set some instruction result high 32bit 1.
>    -follow some change from Richard's suggestion.
>
> v2:
>    -remove patch5 div if x/0 set dividend to 0.
>
>
> Song Gao (3):
>    target/loongarch: bstrins.w src register need EXT_NONE
>    target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
>    softfloat: logB(0) should raise divideByZero exception
>
>   fpu/softfloat-parts.c.inc                     |  1 +
>   target/loongarch/insn_trans/trans_bit.c.inc   | 36 +++++++++++--------
>   .../loongarch/insn_trans/trans_farith.c.inc   | 12 +++----
>   3 files changed, 29 insertions(+), 20 deletions(-)
Applied to loongarch-next.

Thanks.
Song Gao