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Mon, 04 Nov 2024 02:50:51 -0800 (PST) Message-ID: <0e767aee-f9c6-4efe-a91d-40fef98a285b@linaro.org> Date: Mon, 4 Nov 2024 10:50:48 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] target/arm: Add new MMU indexes for AArch32 Secure PL1&0 To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20241101142845.1712482-1-peter.maydell@linaro.org> <20241101142845.1712482-3-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241101142845.1712482-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/1/24 14:28, Peter Maydell wrote: > Our current usage of MMU indexes when EL3 is AArch32 is confused. > Architecturally, when EL3 is AArch32, all Secure code runs under the > Secure PL1&0 translation regime: > * code at EL3, which might be Mon, or SVC, or any of the > other privileged modes (PL1) > * code at EL0 (Secure PL0) > > This is different from when EL3 is AArch64, in which case EL3 is its > own translation regime, and EL1 and EL0 (whether AArch32 or AArch64) > have their own regime. > > We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't > do anything special about Secure PL0, which meant it used the same > ARMMMUIdx_EL10_0 that NonSecure PL0 does. This resulted in a bug > where arm_sctlr() incorrectly picked the NonSecure SCTLR as the > controlling register when in Secure PL0, which meant we were > spuriously generating alignment faults because we were looking at the > wrong SCTLR control bits. > > The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that > we wouldn't honour the PAN bit for Secure PL1, because there's no > equivalent _PAN mmu index for it. > > Fix this by adding two new MMU indexes: > * ARMMMUIdx_E30_0 is for Secure PL0 > * ARMMMUIdx_E30_3_PAN is for Secure PL1 when PAN is enabled > The existing ARMMMUIdx_E3 is used to mean "Secure PL1 without PAN" > (and would be named ARMMMUIdx_E30_3 in an AArch32-centric scheme). > > These extra two indexes bring us up to the maximum of 16 that the > core code can currently support. > > This commit: > * adds the new MMU index handling to the various places > where we deal in MMU index values > * adds assertions that we aren't AArch32 EL3 in a couple of > places that currently use the E10 indexes, to document why > they don't also need to handle the E30 indexes > * documents in a comment why regime_has_2_ranges() doesn't need > updating > > Notes for backporting: this commit depends on the preceding revert of > 4c2c04746932; that revert and this commit should probably be > backported to everywhere that we originally backported 4c2c04746932. > > Cc:qemu-stable@nongnu.org > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2326 > Signed-off-by: Peter Maydell > --- > The regime_has_2_ranges() part is correct but does leave a minor > beartrap for the future if we ever do for some reason need to > identify "has 2 ranges" in an AArch32 codepath... > --- Series: Reviewed-by: Richard Henderson r~