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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id w189sm7896561pfw.157.2020.02.27.11.36.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2020 11:36:43 -0800 (PST) Subject: Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com References: <20200225103508.7651-1-zhiwei_liu@c-sky.com> <20200225103508.7651-3-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <0e806ca9-7991-baf7-58d1-50cddf9ce4ef@linaro.org> Date: Thu, 27 Feb 2020 11:36:41 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200225103508.7651-3-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, linux-csky@vger.kernel.org, wxy194768@alibaba-inc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/25/20 2:35 AM, LIU Zhiwei wrote: > +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t, int64_t, H8, ldsb) > +GEN_VEXT_LD_ELEM(vlsh_v_h, int16_t, int16_t, H2, ldsw) > +GEN_VEXT_LD_ELEM(vlsh_v_w, int16_t, int32_t, H4, ldsw) > +GEN_VEXT_LD_ELEM(vlsh_v_d, int16_t, int64_t, H8, ldsw) > +GEN_VEXT_LD_ELEM(vlsw_v_w, int32_t, int32_t, H4, ldl) > +GEN_VEXT_LD_ELEM(vlsw_v_d, int32_t, int64_t, H8, ldl) > +GEN_VEXT_LD_ELEM(vlse_v_b, int8_t, int8_t, H1, ldsb) > +GEN_VEXT_LD_ELEM(vlse_v_h, int16_t, int16_t, H2, ldsw) > +GEN_VEXT_LD_ELEM(vlse_v_w, int32_t, int32_t, H4, ldl) > +GEN_VEXT_LD_ELEM(vlse_v_d, int64_t, int64_t, H8, ldq) > +GEN_VEXT_LD_ELEM(vlsbu_v_b, uint8_t, uint8_t, H1, ldub) > +GEN_VEXT_LD_ELEM(vlsbu_v_h, uint8_t, uint16_t, H2, ldub) > +GEN_VEXT_LD_ELEM(vlsbu_v_w, uint8_t, uint32_t, H4, ldub) > +GEN_VEXT_LD_ELEM(vlsbu_v_d, uint8_t, uint64_t, H8, ldub) > +GEN_VEXT_LD_ELEM(vlshu_v_h, uint16_t, uint16_t, H2, lduw) > +GEN_VEXT_LD_ELEM(vlshu_v_w, uint16_t, uint32_t, H4, lduw) > +GEN_VEXT_LD_ELEM(vlshu_v_d, uint16_t, uint64_t, H8, lduw) > +GEN_VEXT_LD_ELEM(vlswu_v_w, uint32_t, uint32_t, H4, ldl) > +GEN_VEXT_LD_ELEM(vlswu_v_d, uint32_t, uint64_t, H8, ldl) Why do you need to define new functions identical to the old ones? Are you doing this just to make the names match up? > +GEN_VEXT_ST_ELEM(vssb_v_b, int8_t, H1, stb) > +GEN_VEXT_ST_ELEM(vssb_v_h, int16_t, H2, stb) > +GEN_VEXT_ST_ELEM(vssb_v_w, int32_t, H4, stb) > +GEN_VEXT_ST_ELEM(vssb_v_d, int64_t, H8, stb) > +GEN_VEXT_ST_ELEM(vssh_v_h, int16_t, H2, stw) > +GEN_VEXT_ST_ELEM(vssh_v_w, int32_t, H4, stw) > +GEN_VEXT_ST_ELEM(vssh_v_d, int64_t, H8, stw) > +GEN_VEXT_ST_ELEM(vssw_v_w, int32_t, H4, stl) > +GEN_VEXT_ST_ELEM(vssw_v_d, int64_t, H8, stl) > +GEN_VEXT_ST_ELEM(vsse_v_b, int8_t, H1, stb) > +GEN_VEXT_ST_ELEM(vsse_v_h, int16_t, H2, stw) > +GEN_VEXT_ST_ELEM(vsse_v_w, int32_t, H4, stl) > +GEN_VEXT_ST_ELEM(vsse_v_d, int64_t, H8, stq) Likewise. > +static void vext_st_stride(void *vd, void *v0, target_ulong base, > + target_ulong stride, CPURISCVState *env, uint32_t desc, > + vext_st_elem_fn st_elem, uint32_t esz, uint32_t msz, uintptr_t ra) > +{ > + uint32_t i, k; > + uint32_t nf = vext_nf(desc); > + uint32_t vm = vext_vm(desc); > + uint32_t mlen = vext_mlen(desc); > + uint32_t vlmax = vext_maxsz(desc) / esz; > + > + /* probe every access*/ > + for (i = 0; i < env->vl; i++) { > + if (!vm && !vext_elem_mask(v0, mlen, i)) { > + continue; > + } > + probe_write_access(env, base + stride * i, nf * msz, ra); > + } > + /* store bytes to guest memory */ > + for (i = 0; i < env->vl; i++) { > + k = 0; > + if (!vm && !vext_elem_mask(v0, mlen, i)) { > + continue; > + } > + while (k < nf) { > + target_ulong addr = base + stride * i + k * msz; > + st_elem(env, addr, i + k * vlmax, vd, ra); > + k++; > + } > + } > +} Similar comments wrt unifying the load and store helpers. I'll also note that vext_st_stride and vext_st_us_mask could be unified by passing sizeof(ETYPE) as stride, and vm = true as a parameter. r~