From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
qemu-devel@nongnu.org, Anton Johansson <anjo@rev.ng>
Cc: "Jason Wang" <jasowang@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
devel@lists.libvirt.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Thomas Huth" <thuth@redhat.com>,
qemu-arm@nongnu.org, qemu-ppc@nongnu.org,
"Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>
Subject: Re: [RFC PATCH v3 04/17] hw/net/xilinx_ethlite: Simplify by having configurable endianness
Date: Mon, 11 Nov 2024 13:02:42 +0100 [thread overview]
Message-ID: <0efff9f3-6053-4e2d-80b5-27b4c86da813@linaro.org> (raw)
In-Reply-To: <71a10d65-dd73-4f39-93ee-2c36928f8f4f@redhat.com>
On 8/11/24 16:05, Paolo Bonzini wrote:
> On 11/8/24 16:43, Philippe Mathieu-Daudé wrote:
>> The Xilinx 'ethlite' device was added in commit b43848a100
>> ("xilinx: Add ethlite emulation"), being only built back
>> then for a big-endian MicroBlaze target (see commit 72b675caac
>> "microblaze: Hook into the build-system").
>>
>> I/O endianness access was then clarified in commit d48751ed4f
>> ("xilinx-ethlite: Simplify byteswapping to/from brams"). Here
>> the 'fix' was to use tswap32(). Since the machine was built as
>> big-endian target, tswap32() use means the fix was for a little
>> endian host. While the datasheet (reference added in file header)
>> is not precise about it, we interpret such change as the device
>> expects accesses in big-endian order.
>>
>> Instead of having a double swapping, one in the core memory layer
>> due to DEVICE_NATIVE_ENDIAN and a second one with the tswap calls,
>> allow the machine code to select the proper endianness desired,
>> removing the need of tswap().
>>
>> Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of
>> DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
>> Add the "little-endian" property to select the device endianness,
>> defaulting to little endian.
>> Set the proper endianness on the single machine using the device.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> RFC until I digest Paolo's review from v1:
>> https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/
>
> tl;dr: this works but would break migration compatibility with the
> previous version. If you want to keep that, you need to add
>
>> - r = tswap32(s->regs[addr]);
>> + r = s->regs[addr];
>
> if (s->little_endian_model)
> r = cpu_to_le32(r);
> else
> r = cpu_to_be32(r);
>
>
>> @@ -161,23 +165,26 @@ eth_write(void *opaque, hwaddr addr,
>> break;
>> default:
>
> if (s->little_endian_model)
> r = le32_to_cpu(r);
> else
> r = be32_to_cpu(r);
>
>> - s->regs[addr] = tswap32(value);
>> + s->regs[addr] = value;
>> break;
>
> These pairs ensure that RAM goes through an even number of swaps. I
> don't think they are needed but you decide.
Indeed; I didn't realize it was RAM.
> However, I am wondering if the double MemoryRegionOps are needed *at
> all*. Since petalogix is arguably a little-endian only machine, can you
> just use DEVICE_LITTLE_ENDIAN?
1/ This petalogix machine is actually built in the big-endian binary
2/ As Edgar mentioned elsewhere, Petalogic IP can be synthetized as
big-endian
3/ This machine is used to prove we can remove the TARGET_BIG_ENDIAN
definition and unify big/little endian binaries in our build system.
next prev parent reply other threads:[~2024-11-11 12:03 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-08 15:43 [PATCH v3 00/17] hw/microblaze: Allow running cross-endian vCPUs Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 01/17] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 02/17] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 03/17] hw/intc/xilinx_intc: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-08 15:43 ` [RFC PATCH v3 04/17] hw/net/xilinx_ethlite: Simplify by having configurable endianness Philippe Mathieu-Daudé
2024-11-08 16:05 ` Paolo Bonzini
2024-11-11 12:02 ` Philippe Mathieu-Daudé [this message]
2024-11-08 15:43 ` [RFC PATCH v3 05/17] hw/timer/xilinx_timer: Allow down to 8-bit memory access Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 06/17] hw/timer/xilinx_timer: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 07/17] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 08/17] hw/ssi/xilinx_spi: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 09/17] hw/ssi/xilinx_spips: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 10/17] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors Philippe Mathieu-Daudé
2025-02-04 21:34 ` Philippe Mathieu-Daudé
2025-02-05 0:21 ` Anton Johansson via
2024-11-08 15:43 ` [PATCH v3 11/17] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 12/17] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 13/17] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 14/17] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 15/17] hw/microblaze: Support various endianness for s3adsp1800 machines Philippe Mathieu-Daudé
2024-11-11 7:56 ` Thomas Huth
2024-11-11 11:59 ` Philippe Mathieu-Daudé
2024-11-11 12:16 ` Thomas Huth
2024-11-08 15:43 ` [PATCH v3 16/17] tests/functional: Explicit endianness of microblaze assets Philippe Mathieu-Daudé
2024-11-11 7:51 ` Thomas Huth
2024-11-08 15:43 ` [PATCH v3 17/17] tests/functional: Add microblaze cross-endianness tests Philippe Mathieu-Daudé
2024-11-11 7:57 ` Thomas Huth
2024-11-11 11:54 ` Philippe Mathieu-Daudé
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