From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 to decodetree
Date: Fri, 15 May 2020 19:01:42 -0700 [thread overview]
Message-ID: <0f025a15-5ce6-37f1-9ff7-7cb4f202a320@linaro.org> (raw)
In-Reply-To: <20200515142056.21346-7-peter.maydell@linaro.org>
On 5/15/20 7:20 AM, Peter Maydell wrote:
> Convert the Neon narrowing shifts where op==8 to decodetree:
> * VSHRN
> * VRSHRN
> * VQSHRUN
> * VQRSHRUN
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/neon-dp.decode | 32 ++++++
> target/arm/translate-neon.inc.c | 168 ++++++++++++++++++++++++++++++++
> target/arm/translate.c | 1 +
> 3 files changed, 201 insertions(+)
>
> diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
> index 6456b53a690..f8d19c5819c 100644
> --- a/target/arm/neon-dp.decode
> +++ b/target/arm/neon-dp.decode
> @@ -208,6 +208,10 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
>
> @2reg_shift .... ... . . . ...... .... .... . q:1 . . .... \
> &2reg_shift vm=%vm_dp vd=%vd_dp
> +@2reg_shift_q0 .... ... . . . ...... .... .... . 0 . . .... \
> + &2reg_shift vm=%vm_dp vd=%vd_dp q=0
> +@2reg_shift_q1 .... ... . . . ...... .... .... . 1 . . .... \
> + &2reg_shift vm=%vm_dp vd=%vd_dp q=1
I'm not sure this part makes sense. Correct, you cannot leave the q field
unset and continue to use &2reg_shift, but the insn field q is decode. We wind
up with VSHRN having q=0 and VRSHRN having q=1, which is a distinction without
meaning.
While we could perhaps reasonably set q to a consistent constant, the only
driving reason to do so would be to share code with do_vector_2sh or
do_2shift_env_*.
But since we can't do that, due to the expansion algorithm, I think it would be
better to create a new &2reg_shift_nq that does not contain the q field.
The rest of the code looks good.
r~
next prev parent reply other threads:[~2020-05-16 2:02 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 14:20 [PATCH 00/10] target/arm: Convert 2-reg-shift and 1-reg-imm Neon insns to decodetree Peter Maydell
2020-05-15 14:20 ` [PATCH 01/10] target/arm: Remove unused GEN_NEON_INTEGER_OP macro Peter Maydell
2020-05-15 22:07 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 02/10] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree Peter Maydell
2020-05-15 22:16 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 03/10] target/arm: Convert Neon VSHR 2-reg-shift insns " Peter Maydell
2020-05-15 22:33 ` Richard Henderson
2020-05-15 22:48 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 04/10] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA " Peter Maydell
2020-05-15 22:50 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 05/10] target/arm: Convert VQSHLU, VQSHL " Peter Maydell
2020-05-15 22:55 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 " Peter Maydell
2020-05-16 2:01 ` Richard Henderson [this message]
2020-05-15 14:20 ` [PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 " Peter Maydell
2020-05-16 2:05 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 08/10] target/arm: Convert Neon VSHLL, VMOVL " Peter Maydell
2020-05-16 2:18 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 09/10] target/arm: Convert VCVT fixed-point ops " Peter Maydell
2020-05-16 2:27 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns " Peter Maydell
2020-05-16 2:50 ` Richard Henderson
2020-05-22 14:31 ` Peter Maydell
2020-05-15 21:32 ` [PATCH 00/10] target/arm: Convert 2-reg-shift and 1-reg-imm Neon " no-reply
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