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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id o21sm2420550pjr.37.2020.05.15.19.01.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2020 19:01:44 -0700 (PDT) Subject: Re: [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 to decodetree To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200515142056.21346-1-peter.maydell@linaro.org> <20200515142056.21346-7-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <0f025a15-5ce6-37f1-9ff7-7cb4f202a320@linaro.org> Date: Fri, 15 May 2020 19:01:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200515142056.21346-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/15/20 7:20 AM, Peter Maydell wrote: > Convert the Neon narrowing shifts where op==8 to decodetree: > * VSHRN > * VRSHRN > * VQSHRUN > * VQRSHRUN > > Signed-off-by: Peter Maydell > --- > target/arm/neon-dp.decode | 32 ++++++ > target/arm/translate-neon.inc.c | 168 ++++++++++++++++++++++++++++++++ > target/arm/translate.c | 1 + > 3 files changed, 201 insertions(+) > > diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode > index 6456b53a690..f8d19c5819c 100644 > --- a/target/arm/neon-dp.decode > +++ b/target/arm/neon-dp.decode > @@ -208,6 +208,10 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp > > @2reg_shift .... ... . . . ...... .... .... . q:1 . . .... \ > &2reg_shift vm=%vm_dp vd=%vd_dp > +@2reg_shift_q0 .... ... . . . ...... .... .... . 0 . . .... \ > + &2reg_shift vm=%vm_dp vd=%vd_dp q=0 > +@2reg_shift_q1 .... ... . . . ...... .... .... . 1 . . .... \ > + &2reg_shift vm=%vm_dp vd=%vd_dp q=1 I'm not sure this part makes sense. Correct, you cannot leave the q field unset and continue to use &2reg_shift, but the insn field q is decode. We wind up with VSHRN having q=0 and VRSHRN having q=1, which is a distinction without meaning. While we could perhaps reasonably set q to a consistent constant, the only driving reason to do so would be to share code with do_vector_2sh or do_2shift_env_*. But since we can't do that, due to the expansion algorithm, I think it would be better to create a new &2reg_shift_nq that does not contain the q field. The rest of the code looks good. r~