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dkim=none X-RZG-AUTH: ":LWABbUGmf/p3d3fx281mbpk9zOkHG9L8L9MnY9md4b2JSSHyzkN3ON0Uun6F+zrkVqc/ZmTClqkOE9IdMVvnQ2O6vlW7Z+qlJRBbUq68WzKpoQ==" X-RZG-CLASS-ID: mo00 Received: from [IPv6:2003:c3:9719:3d00:bb52:98ae:ee53:17cd] by smtp.strato.de (RZmta 47.20.3 AUTH) with ESMTPSA id c075a1x29FZNHmz (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Tue, 9 Mar 2021 16:35:23 +0100 (CET) Subject: Re: [PATCH] hw/char: disable ibex uart receive if the buffer is full To: Alistair Francis References: <20210215231528.2718086-1-alexander.wagner@ulal.de> <19c50d64-fe9d-8c72-2002-3586abac821c@ulal.de> From: Alexander Wagner Message-ID: <0f1e36fb-6ac4-b709-a9ba-2754e3f1fe78@ulal.de> Date: Tue, 9 Mar 2021 16:35:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------9D5936DC0AA7FBA8D2BFAF6B" Content-Language: en-US Received-SPF: none client-ip=81.169.146.166; envelope-from=alexander.wagner@ulal.de; helo=mo4-p01-ob.smtp.rzone.de X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Alistair Francis , "qemu-devel@nongnu.org Developers" , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------9D5936DC0AA7FBA8D2BFAF6B Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit On 09.03.21 15:29, Alistair Francis wrote: > On Tue, Mar 9, 2021 at 2:27 AM Alexander Wagner > wrote: >> >> On 08.03.21 14:47, Alistair Francis wrote: >>>> hw/char/ibex_uart.c | 20 +++++++++++++++----- >>>> include/hw/char/ibex_uart.h | 4 ++++ >>>> 2 files changed, 19 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c >>>> index 89f1182c9b..dac09d53d6 100644 >>>> --- a/hw/char/ibex_uart.c >>>> +++ b/hw/char/ibex_uart.c >>>> @@ -66,7 +66,8 @@ static int ibex_uart_can_receive(void *opaque) >>>> { >>>> IbexUartState *s = opaque; >>>> >>>> - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { >>>> + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) >>>> + && !(s->uart_status & R_STATUS_RXFULL_MASK)) { >>>> return 1; >>>> } >>>> >>>> @@ -83,6 +84,8 @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) >>>> >>>> s->uart_status &= ~R_STATUS_RXIDLE_MASK; >>>> s->uart_status &= ~R_STATUS_RXEMPTY_MASK; >>>> + s->uart_status |= R_STATUS_RXFULL_MASK; >>> Doesn't this mean we set RXFULL on every receive? Shouldn't this check >>> the rx_level first? >>> >>> Alistair >> Thank you for having a look! :) >> >> Yes, this is correct. The RXFULL is currently set on every receive. The >> RXFULL is used to indicate to QEMU that the device cannot receive any >> further bytes. >> >> As the FIFO buffers are currently not yet implemented I thought it would >> make sense to behave like the OT UART could only receive one byte at a time. > Ah, good point. > > Can you add a comment where it is set describing that then? > > Alistair > Sure, I just added a comment and emailed this as patch v2. Alex --------------9D5936DC0AA7FBA8D2BFAF6B Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit


On 09.03.21 15:29, Alistair Francis wrote:
On Tue, Mar 9, 2021 at 2:27 AM Alexander Wagner
<alexander.wagner@ulal.de> wrote:

On 08.03.21 14:47, Alistair Francis wrote:
  hw/char/ibex_uart.c         | 20 +++++++++++++++-----
  include/hw/char/ibex_uart.h |  4 ++++
  2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index 89f1182c9b..dac09d53d6 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -66,7 +66,8 @@ static int ibex_uart_can_receive(void *opaque)
  {
      IbexUartState *s = opaque;

-    if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
+    if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
+           && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
          return 1;
      }

@@ -83,6 +84,8 @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)

      s->uart_status &= ~R_STATUS_RXIDLE_MASK;
      s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
+    s->uart_status |= R_STATUS_RXFULL_MASK;
Doesn't this mean we set RXFULL on every receive? Shouldn't this check
the rx_level first?

Alistair
Thank you for having a look! :)

Yes, this is correct. The RXFULL is currently set on every receive. The
RXFULL is used to indicate to QEMU that the device cannot receive any
further bytes.

As the FIFO buffers are currently not yet implemented I thought it would
make sense to behave like the OT UART could only receive one byte at a time.
Ah, good point.

Can you add a comment where it is set describing that then?

Alistair

Sure, I just added a comment and emailed this as patch v2.

Alex
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