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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fc82f2ff6sm21331401f8f.56.2025.09.30.00.30.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Sep 2025 00:30:01 -0700 (PDT) Message-ID: <0f3b1559-1ce2-4201-bd29-3ac131f557cc@linaro.org> Date: Tue, 30 Sep 2025 09:30:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Content-Language: en-US To: Luc Michel Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Francisco Iglesias , "Edgar E . Iglesias" , Alistair Francis , Frederic Konrad , Sai Pavan Boddu References: <20250926070806.292065-1-luc.michel@amd.com> <20250926070806.292065-39-luc.michel@amd.com> <70156c9c-5559-496d-8753-99f1ba5f68d1@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/9/25 08:37, Luc Michel wrote: > Hi Phil, > > On 12:34 Mon 29 Sep , Philippe Mathieu-Daudé wrote: >> On 26/9/25 09:07, Luc Michel wrote: >>> Add the target field in the IRQ descriptor. This allows to target an IRQ >>> to another IRQ controller than the GIC(s). Other supported targets are >>> the PMC PPU1 CPU interrupt controller and the EAM (Error management) >>> device. Those two devices are currently not implemented so IRQs >>> targeting those will be left unconnected. This is in preparation for >>> versal2. >>> >>> Signed-off-by: Luc Michel >>> Reviewed-by: Francisco Iglesias >>> Reviewed-by: Edgar E. Iglesias >>> --- >>> hw/arm/xlnx-versal.c | 41 +++++++++++++++++++++++++++++++++++++++-- >>> 1 file changed, 39 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c >>> index 3d960ed2636..64744401182 100644 >>> --- a/hw/arm/xlnx-versal.c >>> +++ b/hw/arm/xlnx-versal.c >>> @@ -50,18 +50,30 @@ >>> #include "hw/cpu/cluster.h" >>> #include "hw/arm/bsa.h" >>> >>> /* >>> * IRQ descriptor to catch the following cases: >>> + * - An IRQ can either connect to the GICs, to the PPU1 intc, or the the EAM >>> * - Multiple devices can connect to the same IRQ. They are OR'ed together. >>> */ >>> FIELD(VERSAL_IRQ, IRQ, 0, 16) >>> +FIELD(VERSAL_IRQ, TARGET, 16, 2) >>> FIELD(VERSAL_IRQ, ORED, 18, 1) >>> FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */ >>> >>> +typedef enum VersalIrqTarget { >>> + IRQ_TARGET_GIC, >>> + IRQ_TARGET_PPU1, >>> + IRQ_TARGET_EAM, >> >> Maybe declare IRQ_TARGET_RSVD here, > > I'm not convinced. In the future we may need more targets, even more > than 4. In this case we will increase the TARGET field size, probably we > will then have even more reserved fields. I feel the way it's done here > is simple enough to catch all the buggy cases thanks to the default case > in the switch below. Fine then!