From: Richard Henderson <richard.henderson@linaro.org>
To: Sven Schnelle <svens@stackframe.org>
Cc: qemu-devel@nongnu.org, Helge Deller <deller@gmx.de>
Subject: Re: [PATCH] target/hppa: mask upper iaoq bits when returning to narrow mode
Date: Mon, 1 Apr 2024 08:43:58 -1000 [thread overview]
Message-ID: <0f5697e6-da79-424b-866d-40d11b4db0bb@linaro.org> (raw)
In-Reply-To: <20240401145201.2175873-1-svens@stackframe.org>
On 4/1/24 04:52, Sven Schnelle wrote:
> For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
> computation of the new IAOQ value in the signal handler. In the
> current code these bits are not masked when returning to narrow
> mode, causing java to crash.
>
> Signed-off-by: Sven Schnelle <svens@stackframe.org>
> ---
> target/hppa/sys_helper.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c
> index 208e51c086..3bbc2da71b 100644
> --- a/target/hppa/sys_helper.c
> +++ b/target/hppa/sys_helper.c
> @@ -83,6 +83,10 @@ void HELPER(rfi)(CPUHPPAState *env)
> env->iaoq_f = env->cr[CR_IIAOQ];
> env->iaoq_b = env->cr_back[1];
>
> + if (!(env->cr[CR_IPSW] & PSW_W)) {
> + env->iaoq_f &= 0xffffffff;
> + env->iaoq_b &= 0xffffffff;
> + }
This shouldn't be needed, because we are already masking these bits later, in
cpu_get_tb_cpu_state. But I do have some cleanups in this area, and perhaps one of them
matters.
Please try
https://gitlab.com/rth7680/qemu/-/commit/d06e0303595a63565593ab2a5d42f312135b9ded
r~
next prev parent reply other threads:[~2024-04-01 18:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-01 14:52 [PATCH] target/hppa: mask upper iaoq bits when returning to narrow mode Sven Schnelle
2024-04-01 18:43 ` Richard Henderson [this message]
2024-04-01 20:39 ` Sven Schnelle
2024-04-01 20:49 ` Sven Schnelle
2024-04-01 20:56 ` Sven Schnelle
2024-04-01 21:17 ` Richard Henderson
2024-04-01 21:21 ` Richard Henderson
2024-04-01 21:31 ` Sven Schnelle
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