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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id u35sm1521078edc.48.2020.03.05.00.56.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2020 00:56:52 -0800 (PST) Subject: Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking To: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org, groug@kaod.org References: <20200303034351.333043-1-david@gibson.dropbear.id.au> <20200303034351.333043-8-david@gibson.dropbear.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <0f70320c-3b26-cc9e-d695-170bc50c916b@redhat.com> Date: Thu, 5 Mar 2020 09:56:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200303034351.333043-8-david@gibson.dropbear.id.au> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, farosas@linux.ibm.com, Mark Cave-Ayland , Igor Mammedov , paulus@samba.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/3/20 4:43 AM, David Gibson wrote: > When we store the Logical Partitioning Control Register (LPCR) we have a > big switch statement to work out which are valid bits for the cpu model > we're emulating. >=20 > As well as being ugly, this isn't really conceptually correct, since it i= s > based on the mmu_model variable, whereas the LPCR isn't (only) about the > MMU, so mmu_model is basically just acting as a proxy for the cpu model. >=20 > Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM > class. >=20 > Signed-off-by: David Gibson > Reviewed-by: C=C3=A9dric Le Goater > Reviewed-by: Greg Kurz > --- > target/ppc/cpu-qom.h | 1 + > target/ppc/mmu-hash64.c | 36 ++------------------------------- > target/ppc/translate_init.inc.c | 27 +++++++++++++++++++++---- > 3 files changed, 26 insertions(+), 38 deletions(-) >=20 > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index e499575dc8..15d6b54a7d 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass { > uint64_t insns_flags; > uint64_t insns_flags2; > uint64_t msr_mask; > + uint64_t lpcr_mask; /* Available bits in the LPCR */ > uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable = bits */ > powerpc_mmu_t mmu_model; > powerpc_excp_t excp_model; > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c > index caf47ad6fc..0ef330a614 100644 > --- a/target/ppc/mmu-hash64.c > +++ b/target/ppc/mmu-hash64.c > @@ -1095,42 +1095,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cp= u) > =20 > void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) > { > + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env =3D &cpu->env; > - uint64_t lpcr =3D 0; > =20 > - /* Filter out bits */ > - switch (env->mmu_model) { > - case POWERPC_MMU_2_03: /* P5p */ > - lpcr =3D val & (LPCR_RMLS | LPCR_ILE | > - LPCR_LPES0 | LPCR_LPES1 | > - LPCR_RMI | LPCR_HDICE); > - break; > - case POWERPC_MMU_2_06: /* P7 */ > - lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | > - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | > - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | > - LPCR_MER | LPCR_TC | > - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); > - break; > - case POWERPC_MMU_2_07: /* P8 */ > - lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | > - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | > - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE= 1 | > - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | > - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); > - break; > - case POWERPC_MMU_3_00: /* P9 */ > - lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | > - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_A= IL | > - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR= _LD | > - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_= EEE | > - LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPC= R_TC | > - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); > - break; > - default: > - g_assert_not_reached(); > - } > - env->spr[SPR_LPCR] =3D lpcr; > + env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; > ppc_hash64_update_rmls(cpu); > ppc_hash64_update_vrma(cpu); > } > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.= inc.c > index f7acd3d61d..68aa4dfad8 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -8476,6 +8476,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data= ) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > + pcc->lpcr_mask =3D LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | > + LPCR_RMI | LPCR_HDICE; > pcc->mmu_model =3D POWERPC_MMU_2_03; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > @@ -8614,6 +8616,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data= ) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > + pcc->lpcr_mask =3D LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | > + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | > + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | > + LPCR_MER | LPCR_TC | > + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; > + pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; > pcc->mmu_model =3D POWERPC_MMU_2_06; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > @@ -8630,7 +8638,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > pcc->l1_dcache_size =3D 0x8000; > pcc->l1_icache_size =3D 0x8000; > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > - pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; > } > =20 > static void init_proc_POWER8(CPUPPCState *env) > @@ -8785,6 +8792,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data= ) > (1ull << MSR_TS0) | > (1ull << MSR_TS1) | > (1ull << MSR_LE); > + pcc->lpcr_mask =3D LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | > + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | > + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | > + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | > + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; > + pcc->lpcr_pm =3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | > + LPCR_P8_PECE3 | LPCR_P8_PECE4; > pcc->mmu_model =3D POWERPC_MMU_2_07; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > @@ -8802,8 +8816,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > pcc->l1_dcache_size =3D 0x8000; > pcc->l1_icache_size =3D 0x8000; > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > - pcc->lpcr_pm =3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | > - LPCR_P8_PECE3 | LPCR_P8_PECE4; Moving lpcr_pm in the same patch makes review slightly harder, anyway: Reviewed-by: Philippe Mathieu-Daud=C3=A9 > } > =20 > #ifdef CONFIG_SOFTMMU > @@ -8995,6 +9007,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data= ) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > + pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | > + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | > + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | > + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | > + LPCR_DEE | LPCR_OEE)) > + | LPCR_MER | LPCR_GTSE | LPCR_TC | > + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; > + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_= OEE; > pcc->mmu_model =3D POWERPC_MMU_3_00; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; > @@ -9014,7 +9034,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) > pcc->l1_dcache_size =3D 0x8000; > pcc->l1_icache_size =3D 0x8000; > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > - pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_= OEE; > } > =20 > #ifdef CONFIG_SOFTMMU >=20