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From: Paolo Bonzini <pbonzini@redhat.com>
To: Jing Liu <jing2.liu@linux.intel.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v1] x86: Intel AVX512_BF16 feature enabling
Date: Thu, 18 Jul 2019 10:15:53 +0200	[thread overview]
Message-ID: <0f9763fe-af69-e057-9fb1-00527e636fe4@redhat.com> (raw)
In-Reply-To: <c572cdd2-d0f4-2e06-99f8-302b798a04dd@linux.intel.com>

On 18/07/19 06:55, Jing Liu wrote:
>>
>> +            *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7,
>> +                                                count, R_EAX);
> This needs to be firstly checked as follows, otherwise some
> architectures would fail to compile.
> 
> What about hvf and tcg CPUID 07 EAX value?
> 
> +            /* Maximum ECX value for sub-leaves */
> +            if (kvm_enabled()) {
> +                *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7,
> +                                                    count, R_EAX);
> +            } else if (hvf_enabled()) {
> +                *eax = hvf_get_supported_cpuid(0x7, count, R_EAX);
> +            } else {
> +                *eax = 0;
> +            }
> 

Good question.  You need to add a new property, for example
cpuid_level_func7, whose code would be modeled around cpuid_level (and a
field cpuid_min_level_func7 whose code would be modeled around
cpuid_min_level).

Then CPUID[7,0].EAX is set automatically to 0 or 1 depending on whether
BF16 is enabled or not.

Paolo


  reply	other threads:[~2019-07-18  8:16 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11  5:38 [Qemu-devel] [PATCH v1] x86: Intel AVX512_BF16 feature enabling Jing Liu
2019-07-11  5:47 ` no-reply
2019-07-18  4:55 ` Jing Liu
2019-07-18  8:15   ` Paolo Bonzini [this message]
2019-07-19  7:20     ` Jing Liu
2019-07-19  8:10       ` Paolo Bonzini
2019-07-22  2:59         ` Jing Liu
2019-07-22 11:50           ` Paolo Bonzini
2019-07-24 12:05             ` Jing Liu
2019-07-24 12:12               ` Paolo Bonzini

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