From: Artyom Tarasenko <atar4qemu@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Richard Henderson <rth@twiddle.net>,
Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
Date: Wed, 11 Jan 2017 21:19:44 +0100 [thread overview]
Message-ID: <0fcf7eca7c2d3e6bef7846027857da3bd681645d.1484165352.git.atar4qemu@gmail.com> (raw)
In-Reply-To: <cover.1484165352.git.atar4qemu@gmail.com>
In-Reply-To: <cover.1484165352.git.atar4qemu@gmail.com>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target/sparc/translate.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 68677d3..7e399a3 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -3468,7 +3468,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
rs1 = GET_FIELD(insn, 13, 17);
switch (rs1) {
case 0: // hpstate
- // gen_op_rdhpstate();
+ tcg_gen_ld_i64(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, hpstate));
break;
case 1: // htstate
// gen_op_rdhtstate();
@@ -4592,7 +4593,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
switch (rd) {
case 0: // hpstate
- // XXX gen_op_wrhpstate();
+ tcg_gen_st_i64(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ hpstate));
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
--
1.8.3.1
next prev parent reply other threads:[~2017-01-11 20:20 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-11 20:19 [Qemu-devel] [PATCH v2 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervisor flags in TB Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 03/30] target-sparc: use explicit mmu register pointers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 04/30] target-sparc: add UA2005 TTE bit #defines Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register Artyom Tarasenko
2017-01-11 20:19 ` Artyom Tarasenko [this message]
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs " Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 18/30] target-sparc: replace the last tlb entry when no free entries left Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 20/30] target-sparc: implement UA2005 TSB Pointers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 21/30] target-sparc: simplify ultrasparc_tsb_pointer Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 22/30] target-sparc: allow 256M sized pages Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 24/30] target-sparc: add more registers to dump_mmu Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 28/30] target-sparc: implement sun4v RTC Artyom Tarasenko
2017-01-11 20:20 ` [Qemu-devel] [PATCH v2 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Artyom Tarasenko
2017-01-11 20:20 ` [Qemu-devel] [PATCH v2 30/30] target-sparc: fix up niagara machine Artyom Tarasenko
2017-01-26 7:35 ` Markus Armbruster
2017-01-26 9:33 ` Artyom Tarasenko
2017-01-27 14:06 ` Markus Armbruster
2017-01-27 14:27 ` Paolo Bonzini
2017-01-27 14:57 ` Artyom Tarasenko
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