From: Richard Henderson <richard.henderson@linaro.org>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: dbarboza@ventanamicro.com, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations
Date: Sun, 2 Jun 2024 12:45:59 -0500 [thread overview]
Message-ID: <1016c817-d1e0-4dbd-8fd9-921bcdc23a0a@linaro.org> (raw)
In-Reply-To: <20240531174504.281461-6-max.chou@sifive.com>
On 5/31/24 12:44, Max Chou wrote:
> The vector unit-stride load/store instructions (e.g. vle8.v/vse8.v)
> perform continuous load/store. We can replace the corresponding helper
> functions by TCG ops to copy more data at a time with following
> assumptions:
>
> * Perform virtual address resolution once for entire vector at beginning
> * Without mask
> * Without tail agnostic
> * Both host and target are little endian
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Why are you generating all of this inline? This expansion is very large. I would expect
you to get better performance with a helper function.
AGAIN, please see the Arm implementation.
r~
next prev parent reply other threads:[~2024-06-03 5:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 17:44 [RFC PATCH v2 0/6] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 1/6] target/riscv: Separate vector segment " Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 2/6] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 3/6] target/riscv: Inline vext_ldst_us and corresponding function for performance Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 4/6] target/riscv: Add check_probe_[read|write] helper functions Max Chou
2024-05-31 17:44 ` [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations Max Chou
2024-06-02 17:45 ` Richard Henderson [this message]
2024-06-03 15:50 ` Max Chou
2024-06-04 0:58 ` Richard Henderson
2024-05-31 17:44 ` [RFC PATCH v2 6/6] target/riscv: rvv: Optimize vl8re8.v/vs8r.v " Max Chou
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