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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id j40-20020a05600c1c2800b0040e451fd602sm9533800wms.33.2024.01.09.10.17.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jan 2024 10:17:11 -0800 (PST) Message-ID: <102e3be3-a574-4095-a6fa-7d23e7b0b0bc@linaro.org> Date: Tue, 9 Jan 2024 19:17:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/14] hw/arm: Prefer arm_feature(EL3) over object_property_find(has_el3) Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz References: <20240109180930.90793-1-philmd@linaro.org> <20240109180930.90793-10-philmd@linaro.org> <2fccc023-c10d-4d66-8f3a-9e119dd29ffe@linaro.org> In-Reply-To: <2fccc023-c10d-4d66-8f3a-9e119dd29ffe@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/1/24 19:13, Philippe Mathieu-Daudé wrote: > On 9/1/24 19:09, Philippe Mathieu-Daudé wrote: >> The "has_el3" property is added to ARMCPU when the >> ARM_FEATURE_EL3 feature is available. Rather than >> checking whether the QOM property is present, directly >> check the feature. >> >> Suggested-by: Markus Armbruster >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   hw/arm/exynos4210.c   |  4 ++-- >>   hw/arm/integratorcp.c |  5 ++--- >>   hw/arm/realview.c     |  2 +- >>   hw/arm/versatilepb.c  |  5 ++--- >>   hw/arm/xilinx_zynq.c  |  2 +- >>   hw/cpu/a15mpcore.c    | 11 +++++++---- >>   hw/cpu/a9mpcore.c     |  6 +++--- >>   7 files changed, 18 insertions(+), 17 deletions(-) > > >> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c >> index d03f57e579..9355e8443b 100644 >> --- a/hw/cpu/a9mpcore.c >> +++ b/hw/cpu/a9mpcore.c >> @@ -52,7 +52,6 @@ static void a9mp_priv_realize(DeviceState *dev, >> Error **errp) >>       SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, >>                    *wdtbusdev; >>       int i; >> -    bool has_el3; >>       CPUState *cpu0; >>       Object *cpuobj; >> @@ -81,9 +80,10 @@ static void a9mp_priv_realize(DeviceState *dev, >> Error **errp) >>       /* Make the GIC's TZ support match the CPUs. We assume that >>        * either all the CPUs have TZ, or none do. >>        */ >> -    has_el3 = object_property_find(cpuobj, "has_el3") && >> +    if (arm_feature(cpu_env(cpu0), ARM_FEATURE_EL3)) { >>           object_property_get_bool(cpuobj, "has_el3", &error_abort); > > Oops, something is wrong here... This should be: -- >8 -- @@ -84,3 +83,5 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) - has_el3 = object_property_find(cpuobj, "has_el3") && - object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + if (arm_feature(cpu_env(cpu0), ARM_FEATURE_EL3)) { + qdev_prop_set_bit(gicdev, "has-security-extensions", + object_property_get_bool(cpuobj, "has_el3", + &error_abort)); + } --- >> -    qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); >> +        qdev_prop_set_bit(gicdev, "has-security-extensions", true); >> +    } >>       if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { >>           return; >