From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Anton Johansson <anjo@rev.ng>, qemu-devel@nongnu.org
Cc: philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com
Subject: Re: [PATCH v3 04/34] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val()
Date: Wed, 15 Oct 2025 11:14:09 -0700 [thread overview]
Message-ID: <10307c42-8ac3-443d-9046-30c1b7dad12b@linaro.org> (raw)
In-Reply-To: <20251014203512.26282-5-anjo@rev.ng>
On 10/14/25 1:34 PM, Anton Johansson wrote:
> From my understanding the upper_half argument only indicates whether the
> upper or lower 32 bits should be returned, and upper_half will only ever
> be set when MXLEN == 32. However, the function also uses upper_half to
> determine whether the inhibit flags are located in mcyclecfgh or
> mcyclecfg, but this misses the case where MXLEN == 32, upper_half == false
> for TARGET_RISCV32 where we would also need to read the upper half field.
>
> Minor simplifications are also made along with some formatting fixes.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
>
> ---
> NOTE: I've not included any reviewed-bys or modified this patch as it's
> still unclear to me whether this change is correct or not. Alistair
> mentioned that this can get called for MXLEN == 32 and upper_half ==
> false, meaning the lower field would be accessed. I'm sure I'm missing
> something but this is still not clear to me, it seems to me like we
> always want to access the upper half for MXLEN == 32 since that's were
> the inhibit flags are stored.
In case there is a doubt, having an assert for this situation would make
it future proof.
g_assert(!(rv32 && !upper_half));
As well, maybe Alistair can point a call site where this combination is
possible.
> ---
> target/riscv/csr.c | 22 ++++++++++------------
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
next prev parent reply other threads:[~2025-10-15 18:15 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 20:34 [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 01/34] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 02/34] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 03/34] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-16 3:56 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 04/34] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-15 18:14 ` Pierrick Bouvier [this message]
2025-10-16 3:22 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 05/34] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-15 19:12 ` Pierrick Bouvier
2025-10-16 3:05 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 06/34] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 07/34] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 08/34] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 09/34] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-16 4:09 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 10/34] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-15 19:13 ` Pierrick Bouvier
2025-10-16 4:32 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 11/34] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 12/34] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-16 4:33 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 13/34] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-16 4:34 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 14/34] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-16 4:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 15/34] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-16 4:50 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 16/34] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-16 23:45 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 17/34] target/riscv: Fix size of retxh Anton Johansson via
2025-10-16 5:11 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 18/34] target/riscv: Fix size of ssp Anton Johansson via
2025-10-16 5:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 19/34] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-15 20:53 ` Philippe Mathieu-Daudé
2025-10-16 5:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 20/34] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-15 20:52 ` Philippe Mathieu-Daudé
2025-10-16 23:14 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 21/34] target/riscv: Fix size of priv Anton Johansson via
2025-10-16 23:00 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 22/34] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-16 23:15 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 23/34] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 24/34] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 25/34] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-15 20:45 ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 26/34] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-16 23:16 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 27/34] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 28/34] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 29/34] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-15 20:51 ` Philippe Mathieu-Daudé
2025-10-23 10:46 ` Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 30/34] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 31/34] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-15 20:47 ` Philippe Mathieu-Daudé
2025-10-16 23:18 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 32/34] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-15 20:49 ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 33/34] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 34/34] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-16 23:40 ` Alistair Francis
2025-10-15 20:58 ` [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Philippe Mathieu-Daudé
2025-10-16 3:30 ` Alistair Francis
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