From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: david.spickett@linaro.org, qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Stephen Long <steplong@quicinc.com>
Subject: Re: [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp
Date: Thu, 25 Jun 2020 11:59:27 -0700 [thread overview]
Message-ID: <103ac967-fd67-4261-e750-001107b793f9@linaro.org> (raw)
In-Reply-To: <CAFEAcA9+-MoV23aFk_7fcWR29HUREbRt3qaDD59iPvSP2AMrew@mail.gmail.com>
On 6/25/20 5:29 AM, Peter Maydell wrote:
> On Tue, 23 Jun 2020 at 20:37, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Introduce an lvalue macro to wrap target_tlb_bit0.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> +/* Helper for the macros below, validating the argument type. */
>> +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
>> +{
>> + return x;
>> +}
>> +
>> +/*
>> + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
>> + * Using these should be a bit more self-documenting than using the
>> + * generic target bits directly.
>> + */
>> +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
>
> It seems unlikely that we wouldn't get a compile failure if
> we passed something other than a MemTxAttrs* to this macro,
> given the specificity of the field name, but I guess it
> gives us a less confusing compiler error ?
Yes, it's a quite clear error with the function. But you're right, we could
probably get away without it.
r~
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> thanks
> -- PMM
>
next prev parent reply other threads:[~2020-06-25 19:00 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-23 19:36 [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2020-06-23 19:36 ` [PATCH v8 01/45] target/arm: Add isar tests for mte Richard Henderson
2020-06-23 19:36 ` [PATCH v8 02/45] target/arm: Improve masking of SCR RES0 bits Richard Henderson
2020-06-23 19:36 ` [PATCH v8 03/45] target/arm: Add support for MTE to SCTLR_ELx Richard Henderson
2020-06-23 19:36 ` [PATCH v8 04/45] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Richard Henderson
2020-06-23 19:36 ` [PATCH v8 05/45] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Richard Henderson
2020-06-23 19:36 ` [PATCH v8 06/45] target/arm: Add DISAS_UPDATE_NOCHAIN Richard Henderson
2020-06-23 19:36 ` [PATCH v8 07/45] target/arm: Add MTE system registers Richard Henderson
2020-06-23 19:36 ` [PATCH v8 08/45] target/arm: Add MTE bits to tb_flags Richard Henderson
2020-06-23 19:36 ` [PATCH v8 09/45] target/arm: Implement the IRG instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 10/45] target/arm: Revise decoding for disas_add_sub_imm Richard Henderson
2020-06-25 10:16 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 11/45] target/arm: Implement the ADDG, SUBG instructions Richard Henderson
2020-06-25 10:39 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 12/45] target/arm: Implement the GMI instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 13/45] target/arm: Implement the SUBP instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only Richard Henderson
2020-06-25 10:45 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 15/45] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2020-06-25 10:48 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 16/45] target/arm: Implement the STGP instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG Richard Henderson
2020-06-23 19:36 ` [PATCH v8 18/45] target/arm: Simplify DC_ZVA Richard Henderson
2020-06-23 19:36 ` [PATCH v8 19/45] target/arm: Implement the LDGM, STGM, STZGM instructions Richard Henderson
2020-06-23 19:36 ` [PATCH v8 20/45] target/arm: Implement the access tag cache flushes Richard Henderson
2020-06-23 19:36 ` [PATCH v8 21/45] target/arm: Move regime_el to internals.h Richard Henderson
2020-06-23 19:36 ` [PATCH v8 22/45] target/arm: Move regime_tcr " Richard Henderson
2020-06-23 19:36 ` [PATCH v8 23/45] target/arm: Add gen_mte_check1 Richard Henderson
2020-06-23 19:36 ` [PATCH v8 24/45] target/arm: Add gen_mte_checkN Richard Henderson
2020-06-23 19:36 ` [PATCH v8 25/45] target/arm: Implement helper_mte_check1 Richard Henderson
2020-06-25 10:55 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 26/45] target/arm: Implement helper_mte_checkN Richard Henderson
2020-06-23 19:36 ` [PATCH v8 27/45] target/arm: Add helper_mte_check_zva Richard Henderson
2020-06-23 19:36 ` [PATCH v8 28/45] target/arm: Use mte_checkN for sve unpredicated loads Richard Henderson
2020-06-25 11:06 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 29/45] target/arm: Use mte_checkN for sve unpredicated stores Richard Henderson
2020-06-25 11:07 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 30/45] target/arm: Use mte_check1 for sve LD1R Richard Henderson
2020-06-25 11:12 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 31/45] target/arm: Tidy trans_LD1R_zpri Richard Henderson
2020-06-25 11:12 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp Richard Henderson
2020-06-25 12:29 ` Peter Maydell
2020-06-25 18:59 ` Richard Henderson [this message]
2020-06-23 19:36 ` [PATCH v8 33/45] target/arm: Add mte helpers for sve scalar + int loads Richard Henderson
2020-06-25 12:36 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 34/45] target/arm: Add mte helpers for sve scalar + int stores Richard Henderson
2020-06-25 12:37 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 35/45] target/arm: Add mte helpers for sve scalar + int ff/nf loads Richard Henderson
2020-06-25 12:38 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 36/45] target/arm: Handle TBI for sve scalar + int memory ops Richard Henderson
2020-06-25 12:40 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 37/45] target/arm: Add mte helpers for sve scatter/gather " Richard Henderson
2020-06-25 12:43 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE Richard Henderson
2020-06-25 12:52 ` Peter Maydell
2020-06-25 16:54 ` Richard Henderson
2020-06-25 17:07 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 39/45] target/arm: Implement data cache set allocation tags Richard Henderson
2020-06-23 19:36 ` [PATCH v8 40/45] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2020-06-23 19:36 ` [PATCH v8 41/45] target/arm: Always pass cacheattr to get_phys_addr Richard Henderson
2020-06-25 12:56 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 42/45] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2020-06-25 12:59 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 43/45] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2020-06-25 13:26 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 44/45] target/arm: Add allocation tag storage for system mode Richard Henderson
2020-06-25 13:03 ` Peter Maydell
2020-06-25 17:02 ` Richard Henderson
2020-06-25 17:09 ` Peter Maydell
2020-06-25 22:16 ` Richard Henderson
2020-06-23 19:36 ` [PATCH v8 45/45] target/arm: Enable MTE Richard Henderson
2020-06-25 13:06 ` Peter Maydell
2020-06-23 19:55 ` [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode Derrick McKee
2020-06-23 20:06 ` Richard Henderson
2020-06-23 20:30 ` no-reply
2020-06-25 13:28 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=103ac967-fd67-4261-e750-001107b793f9@linaro.org \
--to=richard.henderson@linaro.org \
--cc=david.spickett@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=steplong@quicinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).