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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id u19sm25385540pfk.98.2020.06.25.11.59.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2020 11:59:29 -0700 (PDT) Subject: Re: [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp To: Peter Maydell References: <20200623193658.623279-1-richard.henderson@linaro.org> <20200623193658.623279-33-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <103ac967-fd67-4261-e750-001107b793f9@linaro.org> Date: Thu, 25 Jun 2020 11:59:27 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david.spickett@linaro.org, qemu-arm , QEMU Developers , Stephen Long Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/20 5:29 AM, Peter Maydell wrote: > On Tue, 23 Jun 2020 at 20:37, Richard Henderson > wrote: >> >> Introduce an lvalue macro to wrap target_tlb_bit0. >> >> Signed-off-by: Richard Henderson >> +/* Helper for the macros below, validating the argument type. */ >> +static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) >> +{ >> + return x; >> +} >> + >> +/* >> + * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. >> + * Using these should be a bit more self-documenting than using the >> + * generic target bits directly. >> + */ >> +#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) > > It seems unlikely that we wouldn't get a compile failure if > we passed something other than a MemTxAttrs* to this macro, > given the specificity of the field name, but I guess it > gives us a less confusing compiler error ? Yes, it's a quite clear error with the function. But you're right, we could probably get away without it. r~ > > Reviewed-by: Peter Maydell > > thanks > -- PMM >