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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"mjc@sifive.com" <mjc@sifive.com>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config
Date: Wed, 10 Oct 2018 21:10:15 +0200	[thread overview]
Message-ID: <103d900d-b0f6-3dab-f543-14fbc30cf519@redhat.com> (raw)
In-Reply-To: <1813e888a55667b7097df2a75fa626c98390240d.1539023064.git.alistair.francis@wdc.com>

On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
> 
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  hw/riscv/virt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 005169eabc..6bd723dc3a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
>      serial_mm_init(system_memory, memmap[VIRT_UART0].base,
>          0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
>          serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> +    g_free(plic_hart_config);
>  }
>  
>  static void riscv_virt_board_machine_init(MachineClass *mc)
> 

  reply	other threads:[~2018-10-10 19:10 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs Alistair Francis
2018-10-10 20:03   ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
2018-10-10 19:07   ` Philippe Mathieu-Daudé
2018-10-10 20:03   ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions Alistair Francis
2018-10-10 20:03   ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
2018-10-10 19:10   ` Philippe Mathieu-Daudé [this message]
2018-10-10 20:03   ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
2018-10-10 19:06   ` Philippe Mathieu-Daudé
2018-10-10 20:03   ` Palmer Dabbelt
2018-10-10 17:49 ` [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Palmer Dabbelt
2018-10-10 18:10   ` Peter Maydell
2018-10-10 18:14     ` Alistair
2018-10-10 18:22     ` Palmer Dabbelt
2018-10-11  9:34       ` Peter Maydell
2018-10-12  0:11         ` Palmer Dabbelt
2018-10-11 20:52       ` Michael Clark
2018-10-12  9:34         ` Peter Maydell
2018-10-15 20:28           ` Palmer Dabbelt
2018-10-16  8:05             ` Peter Maydell
2018-10-16 18:35               ` Palmer Dabbelt

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