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Subject: Re: [Qemu-devel] [ADD] tests for PPC target.
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To: qemu-devel@nongnu.org

target-ppc__tests__ppc-test.c.diff

This program intends to test qemu PPC target,
executing a lot of different instructions and dumping
the CPU state.

diff -urNbB -x CVS qemu-current/target-ppc/tests/ppc-test.c qemu/target-ppc/tests/ppc-test.c
--- qemu-current/target-ppc/tests/ppc-test.c	Thu Jan  1 01:00:00 1970
+++ qemu/target-ppc/tests/ppc-test.c	Wed Nov 12 10:40:26 2003
@@ -0,0 +1,3291 @@
+/* Wonderfull micro libc */
+int errno;
+
+#define NULL ((void *)0)
+
+#define O_ACCMODE          0003
+#define O_RDONLY             00
+#define O_WRONLY             01
+#define O_RDWR               02
+#define O_CREAT            0100 /* not fcntl */
+
+#define __NR_exit                 1
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_unlink              10
+#define __NR_sync                36
+#define __NR_fsync              118
+
+unsigned long *__sp;
+register long r16  __asm__ ("r16");
+register long r17  __asm__ ("r17");
+register long r18  __asm__ ("r18");
+register long r19  __asm__ ("r19");
+register long r20  __asm__ ("r20");
+register long r21  __asm__ ("r21");
+
+unsigned char buffer[65536];
+
+#define __syscall_nr(nr, type, name, args...)                           \
+        unsigned long __sc_ret, __sc_err = 0;                           \
+        {                                                               \
+                register unsigned long __sc_0  __asm__ ("r0");          \
+                register unsigned long __sc_3  __asm__ ("r3");          \
+                register unsigned long __sc_4  __asm__ ("r4");          \
+                register unsigned long __sc_5  __asm__ ("r5");          \
+                register unsigned long __sc_6  __asm__ ("r6");          \
+                register unsigned long __sc_7  __asm__ ("r7");          \
+                                                                        \
+                __sc_loadargs_##nr(name, args);                         \
+                __asm__ __volatile__                                    \
+                        ("sc           \n\t"                            \
+                         "mfcr %0      "                                \
+                        : "=&r" (__sc_0),                               \
+                          "=&r" (__sc_3),  "=&r" (__sc_4),              \
+                          "=&r" (__sc_5),  "=&r" (__sc_6),              \
+                          "=&r" (__sc_7)                                \
+                        : __sc_asm_input_##nr                           \
+                        : "cr0", "ctr", "memory",                       \
+                          "r8", "r9", "r10","r11", "r12");              \
+                __sc_ret = __sc_3;                                      \
+        }                                                               \
+        if (__sc_err & 0x10000000)                                      \
+        {                                                               \
+                errno = __sc_ret;                                       \
+                __sc_ret = -1;                                          \
+        }                                                               \
+        return (type) __sc_ret
+
+#define __sc_loadargs_0(name, dummy...)                                 \
+        __sc_0 = __NR_##name
+#define __sc_loadargs_1(name, arg1)                                     \
+        __sc_loadargs_0(name);                                          \
+        __sc_3 = (unsigned long) (arg1)
+#define __sc_loadargs_2(name, arg1, arg2)                               \
+        __sc_loadargs_1(name, arg1);                                    \
+        __sc_4 = (unsigned long) (arg2)
+#define __sc_loadargs_3(name, arg1, arg2, arg3)                         \
+        __sc_loadargs_2(name, arg1, arg2);                              \
+        __sc_5 = (unsigned long) (arg3)
+#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4)                   \
+        __sc_loadargs_3(name, arg1, arg2, arg3);                        \
+        __sc_6 = (unsigned long) (arg4)
+#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5)             \
+        __sc_loadargs_4(name, arg1, arg2, arg3, arg4);                  \
+        __sc_7 = (unsigned long) (arg5)
+
+#define __sc_asm_input_0 "0" (__sc_0)
+#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
+#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
+#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
+#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
+#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
+
+#define _syscall0(type,name)                                            \
+type name(void)                                                         \
+{                                                                       \
+        __syscall_nr(0, type, name);                                    \
+}
+
+#define _syscall1(type,name,type1,arg1)                                 \
+type name(type1 arg1)                                                   \
+{                                                                       \
+        __syscall_nr(1, type, name, arg1);                              \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2)                      \
+type name(type1 arg1, type2 arg2)                                       \
+{                                                                       \
+        __syscall_nr(2, type, name, arg1, arg2);                        \
+}
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
+type name(type1 arg1, type2 arg2, type3 arg3)                           \
+{                                                                       \
+        __syscall_nr(3, type, name, arg1, arg2, arg3);                  \
+}
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4)               \
+{                                                                       \
+        __syscall_nr(4, type, name, arg1, arg2, arg3, arg4);            \
+}
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)   \
+{                                                                       \
+        __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
+}
+
+_syscall1(void, exit, int, status);
+static inline _syscall3(int, read, int, fd, void *, buf, int, count);
+static inline _syscall3(int, write, int, fd, const void *, buf, int, count);
+static inline _syscall3(int, open, const char *, pathname, int, flags, int, mode);
+static inline _syscall1(int, close, int, fd);
+static inline _syscall1(int, unlink, const char *, pathname);
+static inline _syscall0(int, sync);
+static inline _syscall1(int, fsync, int, fd);
+
+static const char logfname[] = "/tmp/ppc-test.log";
+static const char first_mess[] = "PPC testsuite\n";
+static const char test_mess[] = "------------------------------\n";
+static const char sep_mess[] = " ---\n";
+static const char error_mess[] = "TESTSUITE IS BUGGY ! \n";
+static const char test1_err[] = "One operand tests error\n";
+static const char test2_err[] = "Two operands tests error\n";
+static const char testi_err[] =
+"Two operands with 16 bits immediate tests error\n";
+static const char testm_err[] = "Misc tests error\n";
+static const char part1_err[] = "Part 1 failed\n";
+static const char part2_err[] = "Part 2 failed\n";
+static const char part3_err[] = "Part 3 failed\n";
+static const char part4_err[] = "Part 4 failed\n";
+
+static int strlen (const char *string)
+{
+    int len;
+
+    for (len = 0; string[len] != '\0'; len++)
+        continue;
+
+    return len;
+}
+
+static int outstr (int fd, const char *string, int len)
+{
+    return write(fd, string, len);
+}
+
+static int outhex (int fd, unsigned long value)
+{
+    char tmpbuf[9], *pos = tmpbuf;
+    unsigned long tmp;
+    int i;
+
+    for (i = 28; i >= 0; i -=4 , pos++) {
+        tmp = (value >> i) & 0xf;
+        if (tmp < 0xa) {
+            *pos = '0' + tmp;
+        } else {
+            *pos = ('a' - 10) + tmp;
+        }
+    }
+    *pos = '\0';
+
+    return write(fd, tmpbuf, 8);
+}
+
+static inline void dump_ppc_state (int logfile)
+{
+    unsigned long LR, CTR, XER, CR;
+
+    __asm__ __volatile__ ("mflr  %0 ; "
+                          "mfctr %1 ; "
+                          "mfxer %2 ; "
+                          "mfcr  %3 ; "
+                          : "=r"(LR), "=r"(CTR), "=r"(XER), "=r"(CR));
+    /* Don't dump LR: this causes differences between native and
+     * emulated process in the log file...
+     */
+//    outstr(logfile, "LR=0x", 5);
+//    outhex(logfile, LR);
+    outstr(logfile, " CTR=0x", 7);
+    outhex(logfile, CTR);
+    outstr(logfile, " XER=0x", 7);
+    outhex(logfile, XER);
+    outstr(logfile, " CR=0x", 6);
+    outhex(logfile, CR);
+    outstr(logfile, "\n", 1);
+    outstr(logfile, "GPR 16: 0x", 10);
+    outhex(logfile, r16);
+    outstr(logfile, " 0x", 3);
+    outhex(logfile, r17);
+    outstr(logfile, " 0x", 3);
+    outhex(logfile, r18);
+    outstr(logfile, " 0x", 3);
+    outhex(logfile, r19);
+    outstr(logfile, " 0x", 3);
+    outhex(logfile, r20);
+    outstr(logfile, " 0x", 3);
+    outhex(logfile, r21);
+    outstr(logfile, "\n", 1);
+}
+
+static inline void init_ppc (int xer)
+{
+    unsigned long LR = 0, CTR = 0, XER = xer << 29, CR = 0;
+
+    r16 = 0;
+    r17 = 0;
+    r18 = 0;
+    r19 = 0;
+    r20 = 0;
+    r21 = 0;
+    __asm__ __volatile__ ("mtlr  %0 ; "
+                          "mtctr %1 ; "
+                          "mtxer %2 ; "
+                          "mtcr  %3 ; "
+                          :: "r"(LR), "r"(CTR), "r"(XER), "r"(CR));
+}
+
+static inline __volatile__ void flush_icache (void *addr)
+{
+    /* flush icache */
+    __asm__ __volatile__ ("dcbst 0,%0"
+                          :: "r"(addr)
+                          : "memory");
+    __asm__ __volatile__ ("sync"
+                          ::: "memory");
+    __asm__ __volatile__ ("icbi 0,%0"
+                          :: "r"(addr)
+                          : "memory");
+    __asm__ __volatile__ ("sync"
+                          ::: "memory");
+    __asm__ __volatile__ ("isync"
+                          ::: "memory");
+}
+
+static inline __volatile__ void patch_imm16 (void *dst, void *src, int imm16)
+{
+    *((unsigned long *)dst + 0) =
+        ((*((unsigned long *)src + 0)) & 0xFFFF0000) | (imm16 & 0x0000FFFF);
+    *((unsigned long *)dst + 1) = *((unsigned long *)src + 1);
+}
+
+/* One operand opcodes */
+/* Integer arithmetic tests */
+static void test_addme (void)
+{
+    __asm__ __volatile__ ("addme 17, 16");
+}
+
+static void test_addme_ (void)
+{
+    __asm__ __volatile__ ("addme. 17, 16");
+}
+
+static void test_addmeo (void)
+{
+    __asm__ __volatile__ ("addmeo 17, 16");
+}
+
+static void test_addmeo_ (void)
+{
+    __asm__ __volatile__ ("addmeo. 17, 16");
+}
+
+static void test_addze (void)
+{
+    __asm__ __volatile__ ("addze 17, 16");
+}
+
+static void test_addze_ (void)
+{
+    __asm__ __volatile__ ("addze. 17, 16");
+}
+
+static void test_addzeo (void)
+{
+    __asm__ __volatile__ ("addzeo 17, 16");
+}
+
+static void test_addzeo_ (void)
+{
+    __asm__ __volatile__ ("addzeo. 17, 16");
+}
+
+static void test_neg (void)
+{
+    __asm__ __volatile__ ("neg 17, 16");
+}
+
+static void test_neg_ (void)
+{
+    __asm__ __volatile__ ("neg. 17, 16");
+}
+
+static void test_nego (void)
+{
+    __asm__ __volatile__ ("nego 17, 16");
+}
+
+static void test_nego_ (void)
+{
+    __asm__ __volatile__ ("nego. 17, 16");
+}
+
+static void test_subfme (void)
+{
+    __asm__ __volatile__ ("subfme 17, 16");
+}
+
+static void test_subfme_ (void)
+{
+    __asm__ __volatile__ ("subfme. 17, 16");
+}
+
+static void test_subfmeo (void)
+{
+    __asm__ __volatile__ ("subfmeo 17, 16");
+}
+
+static void test_subfmeo_ (void)
+{
+    __asm__ __volatile__ ("subfmeo. 17, 16");
+}
+
+static void test_subfze (void)
+{
+    __asm__ __volatile__ ("subfze 17, 16");
+}
+
+static void test_subfze_ (void)
+{
+    __asm__ __volatile__ ("subfze. 17, 16");
+}
+
+static void test_subfzeo (void)
+{
+    __asm__ __volatile__ ("subfzeo 17, 16");
+}
+
+static void test_subfzeo_ (void)
+{
+    __asm__ __volatile__ ("subfzeo. 17, 16");
+}
+
+/* Integer logical tests */
+static void test_cntlzw (void)
+{
+    __asm__ __volatile__ ("cntlzw 17, 16");
+}
+
+static void test_cntlzw_ (void)
+{
+    __asm__ __volatile__ ("cntlzw. 17, 16");
+}
+
+static void test_extsb (void)
+{
+    __asm__ __volatile__ ("extsb 17, 16");
+}
+
+static void test_extsb_ (void)
+{
+    __asm__ __volatile__ ("extsb. 17, 16");
+}
+
+static void test_extsh (void)
+{
+    __asm__ __volatile__ ("extsh 17, 16");
+}
+
+static void test_extsh_ (void)
+{
+    __asm__ __volatile__ ("extsh. 17, 16");
+}
+
+/* One operand opcodes with dest=src */
+/* Integer arithmetic tests */
+static void test_addme2 (void)
+{
+    __asm__ __volatile__ ("addme 16, 16");
+}
+
+static void test_addme_2 (void)
+{
+    __asm__ __volatile__ ("addme. 16, 16");
+}
+
+static void test_addmeo2 (void)
+{
+    __asm__ __volatile__ ("addmeo 16, 16");
+}
+
+static void test_addmeo_2 (void)
+{
+    __asm__ __volatile__ ("addmeo. 16, 16");
+}
+
+static void test_addze2 (void)
+{
+    __asm__ __volatile__ ("addze 16, 16");
+}
+
+static void test_addze_2 (void)
+{
+    __asm__ __volatile__ ("addze. 16, 16");
+}
+
+static void test_addzeo2 (void)
+{
+    __asm__ __volatile__ ("addzeo 16, 16");
+}
+
+static void test_addzeo_2 (void)
+{
+    __asm__ __volatile__ ("addzeo. 16, 16");
+}
+
+static void test_neg2 (void)
+{
+    __asm__ __volatile__ ("neg 16, 16");
+}
+
+static void test_neg_2 (void)
+{
+    __asm__ __volatile__ ("neg. 16, 16");
+}
+
+static void test_nego2 (void)
+{
+    __asm__ __volatile__ ("nego 16, 16");
+}
+
+static void test_nego_2 (void)
+{
+    __asm__ __volatile__ ("nego. 16, 16");
+}
+
+static void test_subfme2 (void)
+{
+    __asm__ __volatile__ ("subfme 16, 16");
+}
+
+static void test_subfme_2 (void)
+{
+    __asm__ __volatile__ ("subfme. 16, 16");
+}
+
+static void test_subfmeo2 (void)
+{
+    __asm__ __volatile__ ("subfmeo 16, 16");
+}
+
+static void test_subfmeo_2 (void)
+{
+    __asm__ __volatile__ ("subfmeo. 16, 16");
+}
+
+static void test_subfze2 (void)
+{
+    __asm__ __volatile__ ("subfze 16, 16");
+}
+
+static void test_subfze_2 (void)
+{
+    __asm__ __volatile__ ("subfze. 16, 16");
+}
+
+static void test_subfzeo2 (void)
+{
+    __asm__ __volatile__ ("subfzeo 16, 16");
+}
+
+static void test_subfzeo_2 (void)
+{
+    __asm__ __volatile__ ("subfzeo. 16, 16");
+}
+
+/* Integer logical tests */
+static void test_cntlzw2 (void)
+{
+    __asm__ __volatile__ ("cntlzw 17, 16");
+}
+
+static void test_cntlzw_2 (void)
+{
+    __asm__ __volatile__ ("cntlzw. 17, 16");
+}
+
+static void test_extsb2 (void)
+{
+    __asm__ __volatile__ ("extsb 17, 16");
+}
+
+static void test_extsb_2 (void)
+{
+    __asm__ __volatile__ ("extsb. 17, 16");
+}
+
+static void test_extsh2 (void)
+{
+    __asm__ __volatile__ ("extsh 17, 16");
+}
+
+static void test_extsh_2 (void)
+{
+    __asm__ __volatile__ ("extsh. 17, 16");
+}
+
+/* Two operands opcodes */
+/* Integer arithmetic tests */
+static void test_add (void)
+{
+    __asm__ __volatile__ ("add 18, 16, 17");
+}
+
+static void test_add_ (void)
+{
+    __asm__ __volatile__ ("add. 18, 16, 17");
+}
+
+static void test_addo (void)
+{
+    __asm__ __volatile__ ("addo 18, 16, 17");
+}
+
+static void test_addo_ (void)
+{
+    __asm__ __volatile__ ("addo. 18, 16, 17");
+}
+
+static void test_addc (void)
+{
+    __asm__ __volatile__ ("addc 18, 16, 17");
+}
+
+static void test_addc_ (void)
+{
+    __asm__ __volatile__ ("addc. 18, 16, 17");
+}
+
+static void test_addco (void)
+{
+    __asm__ __volatile__ ("addco 18, 16, 17");
+}
+
+static void test_addco_ (void)
+{
+    __asm__ __volatile__ ("addco. 18, 16, 17");
+}
+
+static void test_adde (void)
+{
+    __asm__ __volatile__ ("adde 18, 16, 17");
+}
+
+static void test_adde_ (void)
+{
+    __asm__ __volatile__ ("adde. 18, 16, 17");
+}
+
+static void test_addeo (void)
+{
+    __asm__ __volatile__ ("addeo 18, 16, 17");
+}
+
+static void test_addeo_ (void)
+{
+    __asm__ __volatile__ ("addeo. 18, 16, 17");
+}
+
+static void test_divw (void)
+{
+    __asm__ __volatile__ ("divw 18, 16, 17");
+}
+
+static void test_divw_ (void)
+{
+    __asm__ __volatile__ ("divw. 18, 16, 17");
+}
+
+static void test_divwo (void)
+{
+    __asm__ __volatile__ ("divwo 18, 16, 17");
+}
+
+static void test_divwo_ (void)
+{
+    __asm__ __volatile__ ("divwo. 18, 16, 17");
+}
+
+static void test_divwu (void)
+{
+    __asm__ __volatile__ ("divwu 18, 16, 17");
+}
+
+static void test_divwu_ (void)
+{
+    __asm__ __volatile__ ("divwu. 18, 16, 17");
+}
+
+static void test_divwuo (void)
+{
+    __asm__ __volatile__ ("divwuo 18, 16, 17");
+}
+
+static void test_divwuo_ (void)
+{
+    __asm__ __volatile__ ("divwuo. 18, 16, 17");
+}
+
+static void test_mulhw (void)
+{
+    __asm__ __volatile__ ("mulhw 18, 16, 17");
+}
+
+static void test_mulhw_ (void)
+{
+    __asm__ __volatile__ ("mulhw. 18, 16, 17");
+}
+
+static void test_mulhwu (void)
+{
+    __asm__ __volatile__ ("mulhwu 18, 16, 17");
+}
+
+static void test_mulhwu_ (void)
+{
+    __asm__ __volatile__ ("mulhwu. 18, 16, 17");
+}
+
+static void test_mullw (void)
+{
+    __asm__ __volatile__ ("mullw 18, 16, 17");
+}
+
+static void test_mullw_ (void)
+{
+    __asm__ __volatile__ ("mullw. 18, 16, 17");
+}
+
+static void test_mullwo (void)
+{
+    __asm__ __volatile__ ("mullwo 18, 16, 17");
+}
+
+static void test_mullwo_ (void)
+{
+    __asm__ __volatile__ ("mullwo. 18, 16, 17");
+}
+
+static void test_subf (void)
+{
+    __asm__ __volatile__ ("subf 18, 16, 17");
+}
+
+static void test_subf_ (void)
+{
+    __asm__ __volatile__ ("subf. 18, 16, 17");
+}
+
+static void test_subfo (void)
+{
+    __asm__ __volatile__ ("subfo 18, 16, 17");
+}
+
+static void test_subfo_ (void)
+{
+    __asm__ __volatile__ ("subfo. 18, 16, 17");
+}
+
+static void test_subfc (void)
+{
+    __asm__ __volatile__ ("subfc 18, 16, 17");
+}
+
+static void test_subfc_ (void)
+{
+    __asm__ __volatile__ ("subfc. 18, 16, 17");
+}
+
+static void test_subfco (void)
+{
+    __asm__ __volatile__ ("subfco 18, 16, 17");
+}
+
+static void test_subfco_ (void)
+{
+    __asm__ __volatile__ ("subfco. 18, 16, 17");
+}
+
+static void test_subfe (void)
+{
+    __asm__ __volatile__ ("subfe 18, 16, 17");
+}
+
+static void test_subfe_ (void)
+{
+    __asm__ __volatile__ ("subfe. 18, 16, 17");
+}
+
+static void test_subfeo (void)
+{
+    __asm__ __volatile__ ("subfeo 18, 16, 17");
+}
+
+static void test_subfeo_ (void)
+{
+    __asm__ __volatile__ ("subfeo. 18, 16, 17");
+}
+
+/* Integer comparison tests */
+static void test_cmp (void)
+{
+    __asm__ __volatile__ ("cmp 2, 16, 17");
+}
+
+static void test_cmpl (void)
+{
+    __asm__ __volatile__ ("cmpl 2, 16, 17");
+}
+
+/* Integer logical tests */
+static void test_and (void)
+{
+    __asm__ __volatile__ ("and 18, 16, 17");
+}
+
+static void test_and_ (void)
+{
+    __asm__ __volatile__ ("and. 18, 16, 17");
+}
+
+static void test_andc (void)
+{
+    __asm__ __volatile__ ("andc 18, 16, 17");
+}
+
+static void test_andc_ (void)
+{
+    __asm__ __volatile__ ("andc. 18, 16, 17");
+}
+
+static void test_eqv (void)
+{
+    __asm__ __volatile__ ("eqv 18, 16, 17");
+}
+
+static void test_eqv_ (void)
+{
+    __asm__ __volatile__ ("eqv. 18, 16, 17");
+}
+
+static void test_nand (void)
+{
+    __asm__ __volatile__ ("nand 18, 16, 17");
+}
+
+static void test_nand_ (void)
+{
+    __asm__ __volatile__ ("nand. 18, 16, 17");
+}
+
+static void test_nor (void)
+{
+    __asm__ __volatile__ ("nor 18, 16, 17");
+}
+
+static void test_nor_ (void)
+{
+    __asm__ __volatile__ ("nor. 18, 16, 17");
+}
+
+static void test_or (void)
+{
+    __asm__ __volatile__ ("or 18, 16, 17");
+}
+
+static void test_or_ (void)
+{
+    __asm__ __volatile__ ("or. 18, 16, 17");
+}
+
+static void test_orc (void)
+{
+    __asm__ __volatile__ ("orc 18, 16, 17");
+}
+
+static void test_orc_ (void)
+{
+    __asm__ __volatile__ ("orc. 18, 16, 17");
+}
+
+static void test_xor (void)
+{
+    __asm__ __volatile__ ("xor 18, 16, 17");
+}
+
+static void test_xor_ (void)
+{
+    __asm__ __volatile__ ("xor. 18, 16, 17");
+}
+
+/* Integer shift */
+static void test_slw (void)
+{
+    __asm__ __volatile__ ("slw 18, 16, 17");
+}
+
+static void test_slw_ (void)
+{
+    __asm__ __volatile__ ("slw. 18, 16, 17");
+}
+
+static void test_sraw (void)
+{
+    __asm__ __volatile__ ("sraw 18, 16, 17");
+}
+
+static void test_sraw_ (void)
+{
+    __asm__ __volatile__ ("sraw. 18, 16, 17");
+}
+
+static void test_srw (void)
+{
+    __asm__ __volatile__ ("srw 18, 16, 17");
+}
+
+static void test_srw_ (void)
+{
+    __asm__ __volatile__ ("srw. 18, 16, 17");
+}
+
+/* Integer rotate */
+static void test_rotlw (void)
+{
+    __asm__ __volatile__ ("rotlw 18, 16, 17");
+}
+
+static void test_rotlw_ (void)
+{
+    __asm__ __volatile__ ("rotlw. 18, 16, 17");
+}
+
+/* Two operands opcodes with src=dest */
+/* Integer arithmetic tests */
+static void test_add2 (void)
+{
+    __asm__ __volatile__ ("add 16, 16, 17");
+}
+
+static void test_add_2 (void)
+{
+    __asm__ __volatile__ ("add. 16, 16, 17");
+}
+
+static void test_addo2 (void)
+{
+    __asm__ __volatile__ ("addo 16, 16, 17");
+}
+
+static void test_addo_2 (void)
+{
+    __asm__ __volatile__ ("addo. 16, 16, 17");
+}
+
+static void test_addc2 (void)
+{
+    __asm__ __volatile__ ("addc 16, 16, 17");
+}
+
+static void test_addc_2 (void)
+{
+    __asm__ __volatile__ ("addc. 16, 16, 17");
+}
+
+static void test_addco2 (void)
+{
+    __asm__ __volatile__ ("addco 16, 16, 17");
+}
+
+static void test_addco_2 (void)
+{
+    __asm__ __volatile__ ("addco. 16, 16, 17");
+}
+
+static void test_adde2 (void)
+{
+    __asm__ __volatile__ ("adde 16, 16, 17");
+}
+
+static void test_adde_2 (void)
+{
+    __asm__ __volatile__ ("adde. 16, 16, 17");
+}
+
+static void test_addeo2 (void)
+{
+    __asm__ __volatile__ ("addeo 16, 16, 17");
+}
+
+static void test_addeo_2 (void)
+{
+    __asm__ __volatile__ ("addeo. 16, 16, 17");
+}
+
+static void test_divw2 (void)
+{
+    __asm__ __volatile__ ("divw 16, 16, 17");
+}
+
+static void test_divw_2 (void)
+{
+    __asm__ __volatile__ ("divw. 16, 16, 17");
+}
+
+static void test_divwo2 (void)
+{
+    __asm__ __volatile__ ("divwo 16, 16, 17");
+}
+
+static void test_divwo_2 (void)
+{
+    __asm__ __volatile__ ("divwo. 16, 16, 17");
+}
+
+static void test_divwu2 (void)
+{
+    __asm__ __volatile__ ("divwu 16, 16, 17");
+}
+
+static void test_divwu_2 (void)
+{
+    __asm__ __volatile__ ("divwu. 16, 16, 17");
+}
+
+static void test_divwuo2 (void)
+{
+    __asm__ __volatile__ ("divwuo 16, 16, 17");
+}
+
+static void test_divwuo_2 (void)
+{
+    __asm__ __volatile__ ("divwuo. 16, 16, 17");
+}
+
+static void test_mulhw2 (void)
+{
+    __asm__ __volatile__ ("mulhw 16, 16, 17");
+}
+
+static void test_mulhw_2 (void)
+{
+    __asm__ __volatile__ ("mulhw. 16, 16, 17");
+}
+
+static void test_mulhwu2 (void)
+{
+    __asm__ __volatile__ ("mulhwu 16, 16, 17");
+}
+
+static void test_mulhwu_2 (void)
+{
+    __asm__ __volatile__ ("mulhwu. 16, 16, 17");
+}
+
+static void test_mullw2 (void)
+{
+    __asm__ __volatile__ ("mullw 16, 16, 17");
+}
+
+static void test_mullw_2 (void)
+{
+    __asm__ __volatile__ ("mullw. 16, 16, 17");
+}
+
+static void test_mullwo2 (void)
+{
+    __asm__ __volatile__ ("mullwo 16, 16, 17");
+}
+
+static void test_mullwo_2 (void)
+{
+    __asm__ __volatile__ ("mullwo. 16, 16, 17");
+}
+
+static void test_subf2 (void)
+{
+    __asm__ __volatile__ ("subf 16, 16, 17");
+}
+
+static void test_subf_2 (void)
+{
+    __asm__ __volatile__ ("subf. 16, 16, 17");
+}
+
+static void test_subfo2 (void)
+{
+    __asm__ __volatile__ ("subfo 16, 16, 17");
+}
+
+static void test_subfo_2 (void)
+{
+    __asm__ __volatile__ ("subfo. 16, 16, 17");
+}
+
+static void test_subfc2 (void)
+{
+    __asm__ __volatile__ ("subfc 16, 16, 17");
+}
+
+static void test_subfc_2 (void)
+{
+    __asm__ __volatile__ ("subfc. 16, 16, 17");
+}
+
+static void test_subfco2 (void)
+{
+    __asm__ __volatile__ ("subfco 16, 16, 17");
+}
+
+static void test_subfco_2 (void)
+{
+    __asm__ __volatile__ ("subfco. 16, 16, 17");
+}
+
+static void test_subfe2 (void)
+{
+    __asm__ __volatile__ ("subfe 16, 16, 17");
+}
+
+static void test_subfe_2 (void)
+{
+    __asm__ __volatile__ ("subfe. 16, 16, 17");
+}
+
+static void test_subfeo2 (void)
+{
+    __asm__ __volatile__ ("subfeo 16, 16, 17");
+}
+
+static void test_subfeo_2 (void)
+{
+    __asm__ __volatile__ ("subfeo. 16, 16, 17");
+}
+
+/* Integer logical tests */
+static void test_and2 (void)
+{
+    __asm__ __volatile__ ("and 16, 16, 17");
+}
+
+static void test_and_2 (void)
+{
+    __asm__ __volatile__ ("and. 16, 16, 17");
+}
+
+static void test_andc2 (void)
+{
+    __asm__ __volatile__ ("andc 16, 16, 17");
+}
+
+static void test_andc_2 (void)
+{
+    __asm__ __volatile__ ("andc. 16, 16, 17");
+}
+
+static void test_eqv2 (void)
+{
+    __asm__ __volatile__ ("eqv 16, 16, 17");
+}
+
+static void test_eqv_2 (void)
+{
+    __asm__ __volatile__ ("eqv. 16, 16, 17");
+}
+
+static void test_nand2 (void)
+{
+    __asm__ __volatile__ ("nand 16, 16, 17");
+}
+
+static void test_nand_2 (void)
+{
+    __asm__ __volatile__ ("nand. 16, 16, 17");
+}
+
+static void test_nor2 (void)
+{
+    __asm__ __volatile__ ("nor 16, 16, 17");
+}
+
+static void test_nor_2 (void)
+{
+    __asm__ __volatile__ ("nor. 16, 16, 17");
+}
+
+static void test_or2 (void)
+{
+    __asm__ __volatile__ ("or 16, 16, 17");
+}
+
+static void test_or_2 (void)
+{
+    __asm__ __volatile__ ("or. 16, 16, 17");
+}
+
+static void test_orc2 (void)
+{
+    __asm__ __volatile__ ("orc 16, 16, 17");
+}
+
+static void test_orc_2 (void)
+{
+    __asm__ __volatile__ ("orc. 16, 16, 17");
+}
+
+static void test_xor2 (void)
+{
+    __asm__ __volatile__ ("xor 16, 16, 17");
+}
+
+static void test_xor_2 (void)
+{
+    __asm__ __volatile__ ("xor. 16, 16, 17");
+}
+
+/* Integer shift */
+static void test_slw2 (void)
+{
+    __asm__ __volatile__ ("slw 16, 16, 17");
+}
+
+static void test_slw_2 (void)
+{
+    __asm__ __volatile__ ("slw. 16, 16, 17");
+}
+
+static void test_sraw2 (void)
+{
+    __asm__ __volatile__ ("sraw 16, 16, 17");
+}
+
+static void test_sraw_2 (void)
+{
+    __asm__ __volatile__ ("sraw. 16, 16, 17");
+}
+
+static void test_srw2 (void)
+{
+    __asm__ __volatile__ ("srw 16, 16, 17");
+}
+
+static void test_srw_2 (void)
+{
+    __asm__ __volatile__ ("srw. 16, 16, 17");
+}
+
+/* Integer rotate */
+static void test_rotlw2 (void)
+{
+    __asm__ __volatile__ ("rotlw 16, 16, 17");
+}
+
+static void test_rotlw_2 (void)
+{
+    __asm__ __volatile__ ("rotlw. 16, 16, 17");
+}
+
+/* Two operands opcodes with op1=op2 */
+/* Integer arithmetic tests */
+static void test_add3 (void)
+{
+    __asm__ __volatile__ ("add 17, 16, 16");
+}
+
+static void test_add_3 (void)
+{
+    __asm__ __volatile__ ("add. 17, 16, 16");
+}
+
+static void test_addo3 (void)
+{
+    __asm__ __volatile__ ("addo 17, 16, 16");
+}
+
+static void test_addo_3 (void)
+{
+    __asm__ __volatile__ ("addo. 17, 16, 16");
+}
+
+static void test_addc3 (void)
+{
+    __asm__ __volatile__ ("addc 17, 16, 16");
+}
+
+static void test_addc_3 (void)
+{
+    __asm__ __volatile__ ("addc. 17, 16, 16");
+}
+
+static void test_addco3 (void)
+{
+    __asm__ __volatile__ ("addco 17, 16, 16");
+}
+
+static void test_addco_3 (void)
+{
+    __asm__ __volatile__ ("addco. 17, 16, 16");
+}
+
+static void test_adde3 (void)
+{
+    __asm__ __volatile__ ("adde 17, 16, 16");
+}
+
+static void test_adde_3 (void)
+{
+    __asm__ __volatile__ ("adde. 17, 16, 16");
+}
+
+static void test_addeo3 (void)
+{
+    __asm__ __volatile__ ("addeo 17, 16, 16");
+}
+
+static void test_addeo_3 (void)
+{
+    __asm__ __volatile__ ("addeo. 17, 16, 16");
+}
+
+static void test_divw3 (void)
+{
+    __asm__ __volatile__ ("divw 17, 16, 16");
+}
+
+static void test_divw_3 (void)
+{
+    __asm__ __volatile__ ("divw. 17, 16, 16");
+}
+
+static void test_divwo3 (void)
+{
+    __asm__ __volatile__ ("divwo 17, 16, 16");
+}
+
+static void test_divwo_3 (void)
+{
+    __asm__ __volatile__ ("divwo. 17, 16, 16");
+}
+
+static void test_divwu3 (void)
+{
+    __asm__ __volatile__ ("divwu 17, 16, 16");
+}
+
+static void test_divwu_3 (void)
+{
+    __asm__ __volatile__ ("divwu. 17, 16, 16");
+}
+
+static void test_divwuo3 (void)
+{
+    __asm__ __volatile__ ("divwuo 17, 16, 16");
+}
+
+static void test_divwuo_3 (void)
+{
+    __asm__ __volatile__ ("divwuo. 17, 16, 16");
+}
+
+static void test_mulhw3 (void)
+{
+    __asm__ __volatile__ ("mulhw 17, 16, 16");
+}
+
+static void test_mulhw_3 (void)
+{
+    __asm__ __volatile__ ("mulhw. 17, 16, 16");
+}
+
+static void test_mulhwu3 (void)
+{
+    __asm__ __volatile__ ("mulhwu 17, 16, 16");
+}
+
+static void test_mulhwu_3 (void)
+{
+    __asm__ __volatile__ ("mulhwu. 17, 16, 16");
+}
+
+static void test_mullw3 (void)
+{
+    __asm__ __volatile__ ("mullw 17, 16, 16");
+}
+
+static void test_mullw_3 (void)
+{
+    __asm__ __volatile__ ("mullw. 17, 16, 16");
+}
+
+static void test_mullwo3 (void)
+{
+    __asm__ __volatile__ ("mullwo 17, 16, 16");
+}
+
+static void test_mullwo_3 (void)
+{
+    __asm__ __volatile__ ("mullwo. 17, 16, 16");
+}
+
+static void test_subf3 (void)
+{
+    __asm__ __volatile__ ("subf 17, 16, 16");
+}
+
+static void test_subf_3 (void)
+{
+    __asm__ __volatile__ ("subf. 17, 16, 16");
+}
+
+static void test_subfo3 (void)
+{
+    __asm__ __volatile__ ("subfo 17, 16, 16");
+}
+
+static void test_subfo_3 (void)
+{
+    __asm__ __volatile__ ("subfo. 17, 16, 16");
+}
+
+static void test_subfc3 (void)
+{
+    __asm__ __volatile__ ("subfc 17, 16, 16");
+}
+
+static void test_subfc_3 (void)
+{
+    __asm__ __volatile__ ("subfc. 17, 16, 16");
+}
+
+static void test_subfco3 (void)
+{
+    __asm__ __volatile__ ("subfco 17, 16, 16");
+}
+
+static void test_subfco_3 (void)
+{
+    __asm__ __volatile__ ("subfco. 17, 16, 16");
+}
+
+static void test_subfe3 (void)
+{
+    __asm__ __volatile__ ("subfe 17, 16, 16");
+}
+
+static void test_subfe_3 (void)
+{
+    __asm__ __volatile__ ("subfe. 17, 16, 16");
+}
+
+static void test_subfeo3 (void)
+{
+    __asm__ __volatile__ ("subfeo 17, 16, 16");
+}
+
+static void test_subfeo_3 (void)
+{
+    __asm__ __volatile__ ("subfeo. 17, 16, 16");
+}
+
+/* Integer comparison tests */
+static void test_cmp3 (void)
+{
+    __asm__ __volatile__ ("cmp 2, 16, 16");
+}
+
+static void test_cmpl3 (void)
+{
+    __asm__ __volatile__ ("cmpl 2, 16, 16");
+}
+
+/* Integer logical tests */
+static void test_and3 (void)
+{
+    __asm__ __volatile__ ("and 17, 16, 16");
+}
+
+static void test_and_3 (void)
+{
+    __asm__ __volatile__ ("and. 17, 16, 16");
+}
+
+static void test_andc3 (void)
+{
+    __asm__ __volatile__ ("andc 17, 16, 16");
+}
+
+static void test_andc_3 (void)
+{
+    __asm__ __volatile__ ("andc. 17, 16, 16");
+}
+
+static void test_eqv3 (void)
+{
+    __asm__ __volatile__ ("eqv 17, 16, 16");
+}
+
+static void test_eqv_3 (void)
+{
+    __asm__ __volatile__ ("eqv. 17, 16, 16");
+}
+
+static void test_nand3 (void)
+{
+    __asm__ __volatile__ ("nand 17, 16, 16");
+}
+
+static void test_nand_3 (void)
+{
+    __asm__ __volatile__ ("nand. 17, 16, 16");
+}
+
+static void test_nor3 (void)
+{
+    __asm__ __volatile__ ("nor 17, 16, 16");
+}
+
+static void test_nor_3 (void)
+{
+    __asm__ __volatile__ ("nor. 17, 16, 16");
+}
+
+static void test_or3 (void)
+{
+    __asm__ __volatile__ ("or 17, 16, 16");
+}
+
+static void test_or_3 (void)
+{
+    __asm__ __volatile__ ("or. 17, 16, 16");
+}
+
+static void test_orc3 (void)
+{
+    __asm__ __volatile__ ("orc 17, 16, 16");
+}
+
+static void test_orc_3 (void)
+{
+    __asm__ __volatile__ ("orc. 17, 16, 16");
+}
+
+static void test_xor3 (void)
+{
+    __asm__ __volatile__ ("xor 17, 16, 16");
+}
+
+static void test_xor_3 (void)
+{
+    __asm__ __volatile__ ("xor. 17, 16, 16");
+}
+
+/* Integer shift */
+static void test_slw3 (void)
+{
+    __asm__ __volatile__ ("slw 17, 16, 16");
+}
+
+static void test_slw_3 (void)
+{
+    __asm__ __volatile__ ("slw. 17, 16, 16");
+}
+
+static void test_sraw3 (void)
+{
+    __asm__ __volatile__ ("sraw 17, 16, 16");
+}
+
+static void test_sraw_3 (void)
+{
+    __asm__ __volatile__ ("sraw. 17, 16, 16");
+}
+
+static void test_srw3 (void)
+{
+    __asm__ __volatile__ ("srw 17, 16, 16");
+}
+
+static void test_srw_3 (void)
+{
+    __asm__ __volatile__ ("srw. 17, 16, 16");
+}
+
+/* Integer rotate */
+static void test_rotlw3 (void)
+{
+    __asm__ __volatile__ ("rotlw 17, 16, 16");
+}
+
+static void test_rotlw_3 (void)
+{
+    __asm__ __volatile__ ("rotlw. 17, 16, 16");
+}
+
+/* Two operands opcodes with op1=op2=dst */
+/* Integer arithmetic tests */
+static void test_add4 (void)
+{
+    __asm__ __volatile__ ("add 16, 16, 16");
+}
+
+static void test_add_4 (void)
+{
+    __asm__ __volatile__ ("add. 16, 16, 16");
+}
+
+static void test_addo4 (void)
+{
+    __asm__ __volatile__ ("addo 16, 16, 16");
+}
+
+static void test_addo_4 (void)
+{
+    __asm__ __volatile__ ("addo. 16, 16, 16");
+}
+
+static void test_addc4 (void)
+{
+    __asm__ __volatile__ ("addc 16, 16, 16");
+}
+
+static void test_addc_4 (void)
+{
+    __asm__ __volatile__ ("addc. 16, 16, 16");
+}
+
+static void test_addco4 (void)
+{
+    __asm__ __volatile__ ("addco 16, 16, 16");
+}
+
+static void test_addco_4 (void)
+{
+    __asm__ __volatile__ ("addco. 16, 16, 16");
+}
+
+static void test_adde4 (void)
+{
+    __asm__ __volatile__ ("adde 16, 16, 16");
+}
+
+static void test_adde_4 (void)
+{
+    __asm__ __volatile__ ("adde. 16, 16, 16");
+}
+
+static void test_addeo4 (void)
+{
+    __asm__ __volatile__ ("addeo 16, 16, 16");
+}
+
+static void test_addeo_4 (void)
+{
+    __asm__ __volatile__ ("addeo. 16, 16, 16");
+}
+
+static void test_divw4 (void)
+{
+    __asm__ __volatile__ ("divw 16, 16, 16");
+}
+
+static void test_divw_4 (void)
+{
+    __asm__ __volatile__ ("divw. 16, 16, 16");
+}
+
+static void test_divwo4 (void)
+{
+    __asm__ __volatile__ ("divwo 16, 16, 16");
+}
+
+static void test_divwo_4 (void)
+{
+    __asm__ __volatile__ ("divwo. 16, 16, 16");
+}
+
+static void test_divwu4 (void)
+{
+    __asm__ __volatile__ ("divwu 16, 16, 16");
+}
+
+static void test_divwu_4 (void)
+{
+    __asm__ __volatile__ ("divwu. 16, 16, 16");
+}
+
+static void test_divwuo4 (void)
+{
+    __asm__ __volatile__ ("divwuo 16, 16, 16");
+}
+
+static void test_divwuo_4 (void)
+{
+    __asm__ __volatile__ ("divwuo. 16, 16, 16");
+}
+
+static void test_mulhw4 (void)
+{
+    __asm__ __volatile__ ("mulhw 16, 16, 16");
+}
+
+static void test_mulhw_4 (void)
+{
+    __asm__ __volatile__ ("mulhw. 16, 16, 16");
+}
+
+static void test_mulhwu4 (void)
+{
+    __asm__ __volatile__ ("mulhwu 16, 16, 16");
+}
+
+static void test_mulhwu_4 (void)
+{
+    __asm__ __volatile__ ("mulhwu. 16, 16, 16");
+}
+
+static void test_mullw4 (void)
+{
+    __asm__ __volatile__ ("mullw 16, 16, 16");
+}
+
+static void test_mullw_4 (void)
+{
+    __asm__ __volatile__ ("mullw. 16, 16, 16");
+}
+
+static void test_mullwo4 (void)
+{
+    __asm__ __volatile__ ("mullwo 16, 16, 16");
+}
+
+static void test_mullwo_4 (void)
+{
+    __asm__ __volatile__ ("mullwo. 16, 16, 16");
+}
+
+static void test_subf4 (void)
+{
+    __asm__ __volatile__ ("subf 16, 16, 16");
+}
+
+static void test_subf_4 (void)
+{
+    __asm__ __volatile__ ("subf. 16, 16, 16");
+}
+
+static void test_subfo4 (void)
+{
+    __asm__ __volatile__ ("subfo 16, 16, 16");
+}
+
+static void test_subfo_4 (void)
+{
+    __asm__ __volatile__ ("subfo. 16, 16, 16");
+}
+
+static void test_subfc4 (void)
+{
+    __asm__ __volatile__ ("subfc 16, 16, 16");
+}
+
+static void test_subfc_4 (void)
+{
+    __asm__ __volatile__ ("subfc. 16, 16, 16");
+}
+
+static void test_subfco4 (void)
+{
+    __asm__ __volatile__ ("subfco 16, 16, 16");
+}
+
+static void test_subfco_4 (void)
+{
+    __asm__ __volatile__ ("subfco. 16, 16, 16");
+}
+
+static void test_subfe4 (void)
+{
+    __asm__ __volatile__ ("subfe 16, 16, 16");
+}
+
+static void test_subfe_4 (void)
+{
+    __asm__ __volatile__ ("subfe. 16, 16, 16");
+}
+
+static void test_subfeo4 (void)
+{
+    __asm__ __volatile__ ("subfeo 16, 16, 16");
+}
+
+static void test_subfeo_4 (void)
+{
+    __asm__ __volatile__ ("subfeo. 16, 16, 16");
+}
+
+/* Integer logical tests */
+static void test_and4 (void)
+{
+    __asm__ __volatile__ ("and 16, 16, 16");
+}
+
+static void test_and_4 (void)
+{
+    __asm__ __volatile__ ("and. 16, 16, 16");
+}
+
+static void test_andc4 (void)
+{
+    __asm__ __volatile__ ("andc 16, 16, 16");
+}
+
+static void test_andc_4 (void)
+{
+    __asm__ __volatile__ ("andc. 16, 16, 16");
+}
+
+static void test_eqv4 (void)
+{
+    __asm__ __volatile__ ("eqv 16, 16, 16");
+}
+
+static void test_eqv_4 (void)
+{
+    __asm__ __volatile__ ("eqv. 16, 16, 16");
+}
+
+static void test_nand4 (void)
+{
+    __asm__ __volatile__ ("nand 16, 16, 16");
+}
+
+static void test_nand_4 (void)
+{
+    __asm__ __volatile__ ("nand. 16, 16, 16");
+}
+
+static void test_nor4 (void)
+{
+    __asm__ __volatile__ ("nor 16, 16, 16");
+}
+
+static void test_nor_4 (void)
+{
+    __asm__ __volatile__ ("nor. 16, 16, 16");
+}
+
+static void test_or4 (void)
+{
+    __asm__ __volatile__ ("or 16, 16, 16");
+}
+
+static void test_or_4 (void)
+{
+    __asm__ __volatile__ ("or. 16, 16, 16");
+}
+
+static void test_orc4 (void)
+{
+    __asm__ __volatile__ ("orc 16, 16, 16");
+}
+
+static void test_orc_4 (void)
+{
+    __asm__ __volatile__ ("orc. 16, 16, 16");
+}
+
+static void test_xor4 (void)
+{
+    __asm__ __volatile__ ("xor 16, 16, 16");
+}
+
+static void test_xor_4 (void)
+{
+    __asm__ __volatile__ ("xor. 16, 16, 16");
+}
+
+/* Integer shift */
+static void test_slw4 (void)
+{
+    __asm__ __volatile__ ("slw 16, 16, 16");
+}
+
+static void test_slw_4 (void)
+{
+    __asm__ __volatile__ ("slw. 16, 16, 16");
+}
+
+static void test_sraw4 (void)
+{
+    __asm__ __volatile__ ("sraw 16, 16, 16");
+}
+
+static void test_sraw_4 (void)
+{
+    __asm__ __volatile__ ("sraw. 16, 16, 16");
+}
+
+static void test_srw4 (void)
+{
+    __asm__ __volatile__ ("srw 16, 16, 16");
+}
+
+static void test_srw_4 (void)
+{
+    __asm__ __volatile__ ("srw. 16, 16, 16");
+}
+
+/* Integer rotate */
+static void test_rotlw4 (void)
+{
+    __asm__ __volatile__ ("rotlw 16, 16, 16");
+}
+
+static void test_rotlw_4 (void)
+{
+    __asm__ __volatile__ ("rotlw. 16, 16, 16");
+}
+
+/* Two operands opcodes with 1 16 bits immediate */
+/* Integer arithmetic tests */
+static void test_addi (void)
+{
+    __asm__ __volatile__ ("addi 17, 16, 0");
+}
+
+static void test_addic (void)
+{
+    __asm__ __volatile__ ("addic 17, 16, 0");
+}
+
+static void test_addic_ (void)
+{
+    __asm__ __volatile__ ("addic. 17, 16, 0");
+}
+
+static void test_addis (void)
+{
+    __asm__ __volatile__ ("addis 17, 16, 0");
+}
+
+static void test_mulli (void)
+{
+    __asm__ __volatile__ ("mulli 17, 16, 0");
+}
+
+static void test_subfic (void)
+{
+    __asm__ __volatile__ ("subfic 17, 16, 0");
+}
+
+static void test_cmpi (void)
+{
+    __asm__ __volatile__ ("cmpi 3, 16, 0");
+}
+
+static void test_cmpli (void)
+{
+    __asm__ __volatile__ ("cmpli 4, 16, 0");
+}
+
+static void test_andi_ (void)
+{
+    __asm__ __volatile__ ("andi. 17, 16, 0");
+}
+
+static void test_andis_ (void)
+{
+    __asm__ __volatile__ ("andis. 17, 16, 0");
+}
+
+static void test_ori (void)
+{
+    __asm__ __volatile__ ("ori 17, 16, 0");
+}
+
+static void test_oris (void)
+{
+    __asm__ __volatile__ ("oris 17, 16, 0");
+}
+
+static void test_xori (void)
+{
+    __asm__ __volatile__ ("xori 17, 16, 0");
+}
+
+static void test_xoris (void)
+{
+    __asm__ __volatile__ ("xoris 17, 16, 0");
+}
+
+/* Two operands opcodes with 1 16 bits immediate with src=dst */
+/* Integer arithmetic tests */
+static void test_addi2 (void)
+{
+    __asm__ __volatile__ ("addi 16, 16, 0");
+}
+
+static void test_addic2 (void)
+{
+    __asm__ __volatile__ ("addic 16, 16, 0");
+}
+
+static void test_addic_2 (void)
+{
+    __asm__ __volatile__ ("addic. 16, 16, 0");
+}
+
+static void test_addis2 (void)
+{
+    __asm__ __volatile__ ("addis 16, 16, 0");
+}
+
+static void test_mulli2 (void)
+{
+    __asm__ __volatile__ ("mulli 16, 16, 0");
+}
+
+static void test_subfic2 (void)
+{
+    __asm__ __volatile__ ("subfic 16, 16, 0");
+}
+
+static void test_andi_2 (void)
+{
+    __asm__ __volatile__ ("andi. 16, 16, 0");
+}
+
+static void test_andis_2 (void)
+{
+    __asm__ __volatile__ ("andis. 16, 16, 0");
+}
+
+static void test_ori2 (void)
+{
+    __asm__ __volatile__ ("ori 16, 16, 0");
+}
+
+static void test_oris2 (void)
+{
+    __asm__ __volatile__ ("oris 16, 16, 0");
+}
+
+static void test_xori2 (void)
+{
+    __asm__ __volatile__ ("xori 16, 16, 0");
+}
+
+static void test_xoris2 (void)
+{
+    __asm__ __volatile__ ("xoris 16, 16, 0");
+}
+
+/* Misc opcodes */
+/* Integer rotate */
+static void test_clrlwi1 (void)
+{
+    __asm__ __volatile__ ("clrlwi 17, 16, 0");
+}
+
+static void test_clrlwi2 (void)
+{
+    __asm__ __volatile__ ("clrlwi 17, 16, 12");
+}
+
+static void test_clrlwi3 (void)
+{
+    __asm__ __volatile__ ("clrlwi 17, 16, 17");
+}
+
+static void test_clrlwi4 (void)
+{
+    __asm__ __volatile__ ("clrlwi 17, 16, 31");
+}
+
+static void test_clrlwi_1 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 17, 16, 0");
+}
+
+static void test_clrlwi_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 17, 16, 12");
+}
+
+static void test_clrlwi_3 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 17, 16, 17");
+}
+
+static void test_clrlwi_4 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 17, 16, 31");
+}
+
+static void test_clrlslwi1 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 0, 0");
+}
+
+static void test_clrlslwi2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 7, 0");
+}
+
+static void test_clrlslwi3 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 31, 0");
+}
+
+static void test_clrlslwi4 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 13, 12");
+}
+
+static void test_clrlslwi5 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 13, 12");
+}
+
+static void test_clrlslwi6 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 31, 17");
+}
+
+static void test_clrlslwi7 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 17, 16, 31, 31");
+}
+
+static void test_clrlslwi_1 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 0, 0");
+}
+
+static void test_clrlslwi_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 7, 0");
+}
+
+static void test_clrlslwi_3 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 31, 0");
+}
+
+static void test_clrlslwi_4 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 13, 12");
+}
+
+static void test_clrlslwi_5 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 13, 12");
+}
+
+static void test_clrlslwi_6 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 31, 17");
+}
+
+static void test_clrlslwi_7 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 17, 16, 31, 31");
+}
+
+static void test_clrrwi (void)
+{
+    __asm__ __volatile__ ("clrrwi 17, 16, 7");
+}
+
+static void test_clrrwi_ (void)
+{
+    __asm__ __volatile__ ("clrrwi. 17, 16, 7");
+}
+
+static void test_extlwi (void)
+{
+    __asm__ __volatile__ ("extlwi 17, 16, 7, 8");
+}
+
+static void test_extrwi_ (void)
+{
+    __asm__ __volatile__ ("extrwi. 17, 16, 7, 8");
+}
+
+static void test_extrwi (void)
+{
+    __asm__ __volatile__ ("extrwi 17, 16, 7, 8");
+}
+
+static void test_extlwi_ (void)
+{
+    __asm__ __volatile__ ("extlwi. 17, 16, 7, 8");
+}
+
+static void test_rotlwi (void)
+{
+    __asm__ __volatile__ ("rotlwi 17, 16, 7");
+}
+
+static void test_rotlwi_ (void)
+{
+    __asm__ __volatile__ ("rotlwi. 17, 16, 7");
+}
+
+static void test_rotrwi (void)
+{
+    __asm__ __volatile__ ("rotrwi 17, 16, 7");
+}
+
+static void test_rotrwi_ (void)
+{
+    __asm__ __volatile__ ("rotrwi. 17, 16, 7");
+}
+
+static void test_slwi (void)
+{
+    __asm__ __volatile__ ("slwi 17, 16, 7");
+}
+
+static void test_slwi_ (void)
+{
+    __asm__ __volatile__ ("slwi. 17, 16, 7");
+}
+
+static void test_srwi (void)
+{
+    __asm__ __volatile__ ("srwi 17, 16, 7");
+}
+
+static void test_srwi_ (void)
+{
+    __asm__ __volatile__ ("srwi. 17, 16, 7");
+}
+
+static void test_rlwnm0 (void)
+{
+    __asm__ __volatile__ ("rlwnm 18, 16, 17, 2, 15");
+}
+
+static void test_rlwnm0_ (void)
+{
+    __asm__ __volatile__ ("rlwnm. 18, 16, 17, 3, 15");
+}
+
+static void test_rlwnm16 (void)
+{
+    __asm__ __volatile__ ("rlwnm 18, 16, 17, 16, 29");
+}
+
+static void test_rlwnm16_ (void)
+{
+    __asm__ __volatile__ ("rlwnm. 18, 16, 17, 16, 29");
+}
+
+/* Misc opcodes */
+/* Integer rotate */
+static void test_clrlwi1_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi 16, 16, 0");
+}
+
+static void test_clrlwi2_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi 16, 16, 12");
+}
+
+static void test_clrlwi3_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi 16, 16, 17");
+}
+
+static void test_clrlwi4_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi 16, 16, 31");
+}
+
+static void test_clrlwi_1_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 16, 16, 0");
+}
+
+static void test_clrlwi_2_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 16, 16, 12");
+}
+
+static void test_clrlwi_3_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 16, 16, 17");
+}
+
+static void test_clrlwi_4_2 (void)
+{
+    __asm__ __volatile__ ("clrlwi. 16, 16, 31");
+}
+
+static void test_clrlslwi1_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 0, 0");
+}
+
+static void test_clrlslwi2_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 7, 0");
+}
+
+static void test_clrlslwi3_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 31, 0");
+}
+
+static void test_clrlslwi4_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 13, 12");
+}
+
+static void test_clrlslwi5_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 13, 12");
+}
+
+static void test_clrlslwi6_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 31, 17");
+}
+
+static void test_clrlslwi7_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi 16, 16, 31, 31");
+}
+
+static void test_clrlslwi_1_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 0, 0");
+}
+
+static void test_clrlslwi_2_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 7, 0");
+}
+
+static void test_clrlslwi_3_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 31, 0");
+}
+
+static void test_clrlslwi_4_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 13, 12");
+}
+
+static void test_clrlslwi_5_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 13, 12");
+}
+
+static void test_clrlslwi_6_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 31, 17");
+}
+
+static void test_clrlslwi_7_2 (void)
+{
+    __asm__ __volatile__ ("clrlslwi. 16, 16, 31, 31");
+}
+
+static void test_clrrwi_2 (void)
+{
+    __asm__ __volatile__ ("clrrwi 16, 16, 7");
+}
+
+static void test_clrrwi__2 (void)
+{
+    __asm__ __volatile__ ("clrrwi. 16, 16, 7");
+}
+
+static void test_extlwi_2 (void)
+{
+    __asm__ __volatile__ ("extlwi 16, 16, 7, 8");
+}
+
+static void test_extrwi__2 (void)
+{
+    __asm__ __volatile__ ("extrwi. 16, 16, 7, 8");
+}
+
+static void test_extrwi_2 (void)
+{
+    __asm__ __volatile__ ("extrwi 16, 16, 7, 8");
+}
+
+static void test_extlwi__2 (void)
+{
+    __asm__ __volatile__ ("extlwi. 16, 16, 7, 8");
+}
+
+static void test_rotlwi_2 (void)
+{
+    __asm__ __volatile__ ("rotlwi 16, 16, 7");
+}
+
+static void test_rotlwi__2 (void)
+{
+    __asm__ __volatile__ ("rotlwi. 16, 16, 7");
+}
+
+static void test_rotrwi_2 (void)
+{
+    __asm__ __volatile__ ("rotrwi 16, 16, 7");
+}
+
+static void test_rotrwi__2 (void)
+{
+    __asm__ __volatile__ ("rotrwi. 16, 16, 7");
+}
+
+static void test_slwi_2 (void)
+{
+    __asm__ __volatile__ ("slwi 16, 16, 7");
+}
+
+static void test_slwi__2 (void)
+{
+    __asm__ __volatile__ ("slwi. 16, 16, 7");
+}
+
+static void test_srwi_2 (void)
+{
+    __asm__ __volatile__ ("srwi 16, 16, 7");
+}
+
+static void test_srwi__2 (void)
+{
+    __asm__ __volatile__ ("srwi. 16, 16, 7");
+}
+
+static void test_rlwnm0_2 (void)
+{
+    __asm__ __volatile__ ("rlwnm 16, 16, 17, 2, 15");
+}
+
+static void test_rlwnm0__2 (void)
+{
+    __asm__ __volatile__ ("rlwnm. 16, 16, 17, 3, 15");
+}
+
+static void test_rlwnm16_2 (void)
+{
+    __asm__ __volatile__ ("rlwnm 16, 16, 17, 16, 29");
+}
+
+static void test_rlwnm16__2 (void)
+{
+    __asm__ __volatile__ ("rlwnm. 16, 16, 17, 16, 29");
+}
+
+static void test_rlwinm1 (void)
+{
+    __asm__ __volatile__ ("rlwinm 17, 16, 1, 31, 0");
+}
+
+static void test_rlwinm2 (void)
+{
+    __asm__ __volatile__ ("rlwinm 17, 16, 1, 0, 15");
+}
+
+static void test_rlwinm3 (void)
+{
+    __asm__ __volatile__ ("rlwinm 17, 16, 15, 15, 30");
+}
+
+static void test_rlwinm4 (void)
+{
+    __asm__ __volatile__ ("rlwinm 17, 16, 31, 31, 31");
+}
+
+static void test_rlwinm_1 (void)
+{
+    __asm__ __volatile__ ("rlwinm. 17, 16, 1, 31, 0");
+}
+
+static void test_rlwinm_2 (void)
+{
+    __asm__ __volatile__ ("rlwinm. 17, 16, 1, 0, 15");
+}
+
+static void test_rlwinm_3 (void)
+{
+    __asm__ __volatile__ ("rlwinm. 17, 16, 15, 15, 30");
+}
+
+static void test_rlwinm_4 (void)
+{
+    __asm__ __volatile__ ("rlwinm. 17, 16, 31, 31, 31");
+}
+
+typedef void (*test_t)(void);
+
+typedef struct tests_t {
+    int flags;
+    const char *name;
+    void *test;
+} tests_t;
+
+enum {
+    FL_NR    = 0x000F,
+    FL_IMM16 = 0x0010,
+    FL_MEM   = 0x0020,
+};
+
+/* One operand tests */
+static tests_t tests_1a[] = {
+    /* Integer arithmetic tests */
+    { 0x0001, "addme", &test_addme, },
+    { 0x0001, "addme.", &test_addme_, },
+    { 0x0001, "addmeo", &test_addmeo, },
+    { 0x0001, "addmeo.", &test_addmeo_, },
+    { 0x0001, "addze", &test_addze, },
+    { 0x0001, "addze.", &test_addze_, },
+    { 0x0001, "addzeo", &test_addzeo, },
+    { 0x0001, "addzeo.", &test_addzeo_, },
+    { 0x0001, "neg", &test_neg, },
+    { 0x0001, "neg.", &test_neg_, },
+    { 0x0001, "nego", &test_nego, },
+    { 0x0001, "nego.", &test_nego_, },
+    { 0x0001, "subfme", &test_subfme, },
+    { 0x0001, "subfme.", &test_subfme_, },
+    { 0x0001, "subfmeo", &test_subfmeo, },
+    { 0x0001, "subfmeo.", &test_subfmeo_, },
+    { 0x0001, "subfze", &test_subfze, },
+    { 0x0001, "subfze.", &test_subfze_, },
+    { 0x0001, "subfzeo", &test_subfzeo, },
+    { 0x0001, "subfzeo.", &test_subfzeo_, },
+    /* Integer logical tests */
+    { 0x0001, "cntlzw", &test_cntlzw, },
+    { 0x0001, "cntlzw.", &test_cntlzw_, },
+    { 0x0001, "extsb", &test_extsb, },
+    { 0x0001, "extsb.", &test_extsb_, },
+    { 0x0001, "extsh", &test_extsh, },
+    { 0x0001, "extsh.", &test_extsh_, },
+    { -1, NULL, NULL, },
+};
+
+/* One operand tests with dest=src */
+static tests_t tests_1b[] = {
+    /* Integer arithmetic tests */
+    { 0x0001, "addme 2", &test_addme2, },
+    { 0x0001, "addme. 2", &test_addme_2, },
+    { 0x0001, "addmeo 2", &test_addmeo2, },
+    { 0x0001, "addmeo. 2", &test_addmeo_2, },
+    { 0x0001, "addze 2", &test_addze2, },
+    { 0x0001, "addze. 2", &test_addze_2, },
+    { 0x0001, "addzeo 2", &test_addzeo2, },
+    { 0x0001, "addzeo. 2", &test_addzeo_2, },
+    { 0x0001, "neg 2", &test_neg2, },
+    { 0x0001, "neg. 2", &test_neg_2, },
+    { 0x0001, "nego 2", &test_nego2, },
+    { 0x0001, "nego. 2", &test_nego_2, },
+    { 0x0001, "subfme 2", &test_subfme2, },
+    { 0x0001, "subfme. 2", &test_subfme_2, },
+    { 0x0001, "subfmeo 2", &test_subfmeo2, },
+    { 0x0001, "subfmeo. 2", &test_subfmeo_2, },
+    { 0x0001, "subfze 2", &test_subfze2, },
+    { 0x0001, "subfze. 2", &test_subfze_2, },
+    { 0x0001, "subfzeo 2", &test_subfzeo2, },
+    { 0x0001, "subfzeo. 2", &test_subfzeo_2, },
+    /* Integer logical tests */
+    { 0x0001, "cntlzw 2", &test_cntlzw2, },
+    { 0x0001, "cntlzw. 2", &test_cntlzw_2, },
+    { 0x0001, "extsb 2", &test_extsb2, },
+    { 0x0001, "extsb. 2", &test_extsb_2, },
+    { 0x0001, "extsh 2", &test_extsh2, },
+    { 0x0001, "extsh. 2", &test_extsh_2, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operands tests */
+static tests_t tests_2a[] = {
+    /* Integer arithmetic tests */
+    { 0x0002, "add", &test_add, },
+    { 0x0002, "add.", &test_add_, },
+    { 0x0002, "addo", &test_addo, },
+    { 0x0002, "addo.", &test_addo_, },
+    { 0x0002, "addc", &test_addc, },
+    { 0x0002, "addc.", &test_addc_, },
+    { 0x0002, "addco", &test_addco, },
+    { 0x0002, "addco.", &test_addco_, },
+    { 0x0002, "adde", &test_adde, },
+    { 0x0002, "adde.", &test_adde_, },
+    { 0x0002, "addeo", &test_addeo, },
+    { 0x0002, "addeo.", &test_addeo_, },
+    { 0x0002, "divw", &test_divw, },
+    { 0x0002, "divw.", &test_divw_, },
+    { 0x0002, "divwo", &test_divwo, },
+    { 0x0002, "divwo.", &test_divwo_, },
+    { 0x0002, "divwu", &test_divwu, },
+    { 0x0002, "divwu.", &test_divwu_, },
+    { 0x0002, "divwuo", &test_divwuo, },
+    { 0x0002, "divwuo.", &test_divwuo_, },
+    { 0x0002, "mulhw", &test_mulhw, },
+    { 0x0002, "mulhw.", &test_mulhw_, },
+    { 0x0002, "mulhwu", &test_mulhwu, },
+    { 0x0002, "mulhwu.", &test_mulhwu_, },
+    { 0x0002, "mullw", &test_mullw, },
+    { 0x0002, "mullw.", &test_mullw_, },
+    { 0x0002, "mullwo", &test_mullwo, },
+    { 0x0002, "mullwo.", &test_mullwo_, },
+    { 0x0002, "subf", &test_subf, },
+    { 0x0002, "subf.", &test_subf_, },
+    { 0x0002, "subfo", &test_subfo, },
+    { 0x0002, "subfo.", &test_subfo_, },
+    { 0x0002, "subfc", &test_subfc, },
+    { 0x0002, "subfc.", &test_subfc_, },
+    { 0x0002, "subfco", &test_subfco, },
+    { 0x0002, "subfco.", &test_subfco_, },
+    { 0x0002, "subfe", &test_subfe, },
+    { 0x0002, "subfe.", &test_subfe_, },
+    { 0x0002, "subfeo", &test_subfeo, },
+    { 0x0002, "subfeo.", &test_subfeo_, },
+    /* Integer comparison tests */
+    { 0x0002, "cmp", &test_cmp, },
+    { 0x0002, "cmpl", &test_cmpl, },
+    /* Integer logical tests */
+    { 0x0002, "and", &test_and, },
+    { 0x0002, "and.", &test_and_, },
+    { 0x0002, "andc", &test_andc, },
+    { 0x0002, "andc.", &test_andc_, },
+    { 0x0002, "eqv", &test_eqv, },
+    { 0x0002, "eqv.", &test_eqv_, },
+    { 0x0002, "nand", &test_nand, },
+    { 0x0002, "nand.", &test_nand_, },
+    { 0x0002, "nor", &test_nor, },
+    { 0x0002, "nor.", &test_nor_, },
+    { 0x0002, "or", &test_or, },
+    { 0x0002, "or.", &test_or_, },
+    { 0x0002, "orc", &test_orc, },
+    { 0x0002, "orc.", &test_orc_, },
+    { 0x0002, "xor", &test_xor, },
+    { 0x0002, "xor.", &test_xor_, },
+    { 0x0002, "rotlw", &test_rotlw, },
+    { 0x0002, "rotlw.", &test_rotlw_, },
+    /* Integer shift */
+    { 0x0002, "slw", &test_slw, },
+    { 0x0002, "slw.", &test_slw_, },
+    { 0x0002, "sraw", &test_sraw, },
+    { 0x0002, "sraw.", &test_sraw_, },
+    { 0x0002, "srw", &test_srw, },
+    { 0x0002, "srw.", &test_srw_, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operands tests with src=dst */
+static tests_t tests_2b[] = {
+    /* Integer arithmetic tests */
+    { 0x0002, "add 2", &test_add2, },
+    { 0x0002, "add. 2", &test_add_2, },
+    { 0x0002, "addo 2", &test_addo2, },
+    { 0x0002, "addo. 2", &test_addo_2, },
+    { 0x0002, "addc 2", &test_addc2, },
+    { 0x0002, "addc. 2", &test_addc_2, },
+    { 0x0002, "addco 2", &test_addco2, },
+    { 0x0002, "addco. 2", &test_addco_2, },
+    { 0x0002, "adde 2", &test_adde2, },
+    { 0x0002, "adde. 2", &test_adde_2, },
+    { 0x0002, "addeo 2", &test_addeo2, },
+    { 0x0002, "addeo. 2", &test_addeo_2, },
+    { 0x0002, "divw 2", &test_divw2, },
+    { 0x0002, "divw. 2", &test_divw_2, },
+    { 0x0002, "divwo 2", &test_divwo2, },
+    { 0x0002, "divwo. 2", &test_divwo_2, },
+    { 0x0002, "divwu 2", &test_divwu2, },
+    { 0x0002, "divwu. 2", &test_divwu_2, },
+    { 0x0002, "divwuo 2", &test_divwuo2, },
+    { 0x0002, "divwuo. 2", &test_divwuo_2, },
+    { 0x0002, "mulhw 2", &test_mulhw2, },
+    { 0x0002, "mulhw. 2", &test_mulhw_2, },
+    { 0x0002, "mulhwu 2", &test_mulhwu2, },
+    { 0x0002, "mulhwu. 2", &test_mulhwu_2, },
+    { 0x0002, "mullw 2", &test_mullw2, },
+    { 0x0002, "mullw. 2", &test_mullw_2, },
+    { 0x0002, "mullwo 2", &test_mullwo2, },
+    { 0x0002, "mullwo. 2", &test_mullwo_2, },
+    { 0x0002, "subf 2", &test_subf2, },
+    { 0x0002, "subf. 2", &test_subf_2, },
+    { 0x0002, "subfo 2", &test_subfo2, },
+    { 0x0002, "subfo. 2", &test_subfo_2, },
+    { 0x0002, "subfc 2", &test_subfc2, },
+    { 0x0002, "subfc. 2", &test_subfc_2, },
+    { 0x0002, "subfco 2", &test_subfco2, },
+    { 0x0002, "subfco. 2", &test_subfco_2, },
+    { 0x0002, "subfe 2", &test_subfe2, },
+    { 0x0002, "subfe. 2", &test_subfe_2, },
+    { 0x0002, "subfeo 2", &test_subfeo2, },
+    { 0x0002, "subfeo. 2", &test_subfeo_2, },
+    /* Integer logical tests */
+    { 0x0002, "and 2", &test_and2, },
+    { 0x0002, "and. 2", &test_and_2, },
+    { 0x0002, "andc 2", &test_andc2, },
+    { 0x0002, "andc. 2", &test_andc_2, },
+    { 0x0002, "eqv 2", &test_eqv2, },
+    { 0x0002, "eqv. 2", &test_eqv_2, },
+    { 0x0002, "nand 2", &test_nand2, },
+    { 0x0002, "nand. 2", &test_nand_2, },
+    { 0x0002, "nor 2", &test_nor2, },
+    { 0x0002, "nor. 2", &test_nor_2, },
+    { 0x0002, "or 2", &test_or2, },
+    { 0x0002, "or. 2", &test_or_2, },
+    { 0x0002, "orc 2", &test_orc2, },
+    { 0x0002, "orc. 2", &test_orc_2, },
+    { 0x0002, "xor 2", &test_xor2, },
+    { 0x0002, "xor. 2", &test_xor_2, },
+    { 0x0002, "rotlw 2", &test_rotlw2, },
+    { 0x0002, "rotlw. 2", &test_rotlw_2, },
+    /* Integer shift */
+    { 0x0002, "slw 2", &test_slw2, },
+    { 0x0002, "slw. 2", &test_slw_2, },
+    { 0x0002, "sraw 2", &test_sraw2, },
+    { 0x0002, "sraw. 2", &test_sraw_2, },
+    { 0x0002, "srw 2", &test_srw2, },
+    { 0x0002, "srw. 2", &test_srw_2, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operands tests with op1=op2 */
+static tests_t tests_2c[] = {
+    /* Integer arithmetic tests */
+    { 0x0001, "add 3", &test_add3, },
+    { 0x0001, "add. 3", &test_add_3, },
+    { 0x0001, "addo 3", &test_addo3, },
+    { 0x0001, "addo. 3", &test_addo_3, },
+    { 0x0001, "addc 3", &test_addc3, },
+    { 0x0001, "addc. 3", &test_addc_3, },
+    { 0x0001, "addco 3", &test_addco3, },
+    { 0x0001, "addco. 3", &test_addco_3, },
+    { 0x0001, "adde 3", &test_adde3, },
+    { 0x0001, "adde. 3", &test_adde_3, },
+    { 0x0001, "addeo 3", &test_addeo3, },
+    { 0x0001, "addeo. 3", &test_addeo_3, },
+    { 0x0001, "divw 3", &test_divw3, },
+    { 0x0001, "divw. 3", &test_divw_3, },
+    { 0x0001, "divwo 3", &test_divwo3, },
+    { 0x0001, "divwo. 3", &test_divwo_3, },
+    { 0x0001, "divwu 3", &test_divwu3, },
+    { 0x0001, "divwu. 3", &test_divwu_3, },
+    { 0x0001, "divwuo 3", &test_divwuo3, },
+    { 0x0001, "divwuo. 3", &test_divwuo_3, },
+    { 0x0001, "mulhw 3", &test_mulhw3, },
+    { 0x0001, "mulhw. 3", &test_mulhw_3, },
+    { 0x0001, "mulhwu 3", &test_mulhwu3, },
+    { 0x0001, "mulhwu. 3", &test_mulhwu_3, },
+    { 0x0001, "mullw 3", &test_mullw3, },
+    { 0x0001, "mullw. 3", &test_mullw_3, },
+    { 0x0001, "mullwo 3", &test_mullwo3, },
+    { 0x0001, "mullwo. 3", &test_mullwo_3, },
+    { 0x0001, "subf 3", &test_subf3, },
+    { 0x0001, "subf. 3", &test_subf_3, },
+    { 0x0001, "subfo 3", &test_subfo3, },
+    { 0x0001, "subfo. 3", &test_subfo_3, },
+    { 0x0001, "subfc 3", &test_subfc3, },
+    { 0x0001, "subfc. 3", &test_subfc_3, },
+    { 0x0001, "subfco 3", &test_subfco3, },
+    { 0x0001, "subfco. 3", &test_subfco_3, },
+    { 0x0001, "subfe 3", &test_subfe3, },
+    { 0x0001, "subfe. 3", &test_subfe_3, },
+    { 0x0001, "subfeo 3", &test_subfeo3, },
+    { 0x0001, "subfeo. 3", &test_subfeo_3, },
+    /* Integer comparison tests */
+    { 0x0001, "cmp 3", &test_cmp3, },
+    { 0x0001, "cmpl 3", &test_cmpl3, },
+    /* Integer logical tests */
+    { 0x0001, "and 3", &test_and3, },
+    { 0x0001, "and. 3", &test_and_3, },
+    { 0x0001, "andc 3", &test_andc3, },
+    { 0x0001, "andc. 3", &test_andc_3, },
+    { 0x0001, "eqv 3", &test_eqv3, },
+    { 0x0001, "eqv. 3", &test_eqv_3, },
+    { 0x0001, "nand 3", &test_nand3, },
+    { 0x0001, "nand. 3", &test_nand_3, },
+    { 0x0001, "nor 3", &test_nor3, },
+    { 0x0001, "nor. 3", &test_nor_3, },
+    { 0x0001, "or 3", &test_or3, },
+    { 0x0001, "or. 3", &test_or_3, },
+    { 0x0001, "orc 3", &test_orc3, },
+    { 0x0001, "orc. 3", &test_orc_3, },
+    { 0x0001, "xor 3", &test_xor3, },
+    { 0x0001, "xor. 3", &test_xor_3, },
+    { 0x0001, "rotlw 3", &test_rotlw3, },
+    { 0x0001, "rotlw. 3", &test_rotlw_3, },
+    /* Integer shift */
+    { 0x0001, "slw 3", &test_slw3, },
+    { 0x0001, "slw. 3", &test_slw_3, },
+    { 0x0001, "sraw 3", &test_sraw3, },
+    { 0x0001, "sraw. 3", &test_sraw_3, },
+    { 0x0001, "srw 3", &test_srw3, },
+    { 0x0001, "srw. 3", &test_srw_3, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operands tests with op1=op2=dst */
+static tests_t tests_2d[] = {
+    /* Integer arithmetic tests */
+    { 0x0001, "add 4", &test_add4, },
+    { 0x0001, "add. 4", &test_add_4, },
+    { 0x0001, "addo 4", &test_addo4, },
+    { 0x0001, "addo. 4", &test_addo_4, },
+    { 0x0001, "addc 4", &test_addc4, },
+    { 0x0001, "addc. 4", &test_addc_4, },
+    { 0x0001, "addco 4", &test_addco4, },
+    { 0x0001, "addco. 4", &test_addco_4, },
+    { 0x0001, "adde 4", &test_adde4, },
+    { 0x0001, "adde. 4", &test_adde_4, },
+    { 0x0001, "addeo 4", &test_addeo4, },
+    { 0x0001, "addeo. 4", &test_addeo_4, },
+    { 0x0001, "divw 4", &test_divw4, },
+    { 0x0001, "divw. 4", &test_divw_4, },
+    { 0x0001, "divwo 4", &test_divwo4, },
+    { 0x0001, "divwo. 4", &test_divwo_4, },
+    { 0x0001, "divwu 4", &test_divwu4, },
+    { 0x0001, "divwu. 4", &test_divwu_4, },
+    { 0x0001, "divwuo 4", &test_divwuo4, },
+    { 0x0001, "divwuo. 4", &test_divwuo_4, },
+    { 0x0001, "mulhw 4", &test_mulhw4, },
+    { 0x0001, "mulhw. 4", &test_mulhw_4, },
+    { 0x0001, "mulhwu 4", &test_mulhwu4, },
+    { 0x0001, "mulhwu. 4", &test_mulhwu_4, },
+    { 0x0001, "mullw 4", &test_mullw4, },
+    { 0x0001, "mullw. 4", &test_mullw_4, },
+    { 0x0001, "mullwo 4", &test_mullwo4, },
+    { 0x0001, "mullwo. 4", &test_mullwo_4, },
+    { 0x0001, "subf 4", &test_subf4, },
+    { 0x0001, "subf. 4", &test_subf_4, },
+    { 0x0001, "subfo 4", &test_subfo4, },
+    { 0x0001, "subfo. 4", &test_subfo_4, },
+    { 0x0001, "subfc 4", &test_subfc4, },
+    { 0x0001, "subfc. 4", &test_subfc_4, },
+    { 0x0001, "subfco 4", &test_subfco4, },
+    { 0x0001, "subfco. 4", &test_subfco_4, },
+    { 0x0001, "subfe 4", &test_subfe4, },
+    { 0x0001, "subfe. 4", &test_subfe_4, },
+    { 0x0001, "subfeo 4", &test_subfeo4, },
+    { 0x0001, "subfeo. 4", &test_subfeo_4, },
+    /* Integer logical tests */
+    { 0x0001, "and 4", &test_and4, },
+    { 0x0001, "and. 4", &test_and_4, },
+    { 0x0001, "andc 4", &test_andc4, },
+    { 0x0001, "andc. 4", &test_andc_4, },
+    { 0x0001, "eqv 4", &test_eqv4, },
+    { 0x0001, "eqv. 4", &test_eqv_4, },
+    { 0x0001, "nand 4", &test_nand4, },
+    { 0x0001, "nand. 4", &test_nand_4, },
+    { 0x0001, "nor 4", &test_nor4, },
+    { 0x0001, "nor. 4", &test_nor_4, },
+    { 0x0001, "or 4", &test_or4, },
+    { 0x0001, "or. 4", &test_or_4, },
+    { 0x0001, "orc 4", &test_orc4, },
+    { 0x0001, "orc. 4", &test_orc_4, },
+    { 0x0001, "xor 4", &test_xor4, },
+    { 0x0001, "xor. 4", &test_xor_4, },
+    { 0x0001, "rotlw 4", &test_rotlw4, },
+    { 0x0001, "rotlw. 4", &test_rotlw_4, },
+    /* Integer shift */
+    { 0x0001, "slw 4", &test_slw4, },
+    { 0x0001, "slw. 4", &test_slw_4, },
+    { 0x0001, "sraw 4", &test_sraw4, },
+    { 0x0001, "sraw. 4", &test_sraw_4, },
+    { 0x0001, "srw 4", &test_srw4, },
+    { 0x0001, "srw. 4", &test_srw_4, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operand with 16 bits immediate tests */
+static tests_t tests_ia[] = {
+    { 0x0002 | FL_IMM16, "addi", &test_addi, },
+    { 0x0002 | FL_IMM16, "addic", &test_addic, },
+    { 0x0002 | FL_IMM16, "addic.", &test_addic_, },
+    { 0x0002 | FL_IMM16, "addis", &test_addis, },
+    { 0x0002 | FL_IMM16, "mulli", &test_mulli, },
+    { 0x0002 | FL_IMM16, "subfic", &test_subfic, },
+    { 0x0002 | FL_IMM16, "cmpi", &test_cmpi, },
+    { 0x0002 | FL_IMM16, "cmpli", &test_cmpli, },
+    { 0x0002 | FL_IMM16, "andi.", &test_andi_, },
+    { 0x0002 | FL_IMM16, "andis.", &test_andis_, },
+    { 0x0002 | FL_IMM16, "ori", &test_ori, },
+    { 0x0002 | FL_IMM16, "oris", &test_oris, },
+    { 0x0002 | FL_IMM16, "xori", &test_xori, },
+    { 0x0002 | FL_IMM16, "xoris", &test_xoris, },
+    { -1, NULL, NULL, },
+};
+
+/* Two operand with 16 bits immediate tests with src=dst*/
+static tests_t tests_ib[] = {
+    { 0x0002 | FL_IMM16, "addi 2", &test_addi2, },
+    { 0x0002 | FL_IMM16, "addic 2", &test_addic2, },
+    { 0x0002 | FL_IMM16, "addic. 2", &test_addic_2, },
+    { 0x0002 | FL_IMM16, "addis 2", &test_addis2, },
+    { 0x0002 | FL_IMM16, "mulli 2", &test_mulli2, },
+    { 0x0002 | FL_IMM16, "subfic 2", &test_subfic2, },
+    { 0x0002 | FL_IMM16, "andi. 2", &test_andi_2, },
+    { 0x0002 | FL_IMM16, "andis. 2", &test_andis_2, },
+    { 0x0002 | FL_IMM16, "ori 2", &test_ori2, },
+    { 0x0002 | FL_IMM16, "oris 2", &test_oris2, },
+    { 0x0002 | FL_IMM16, "xori 2", &test_xori2, },
+    { 0x0002 | FL_IMM16, "xoris 2", &test_xoris2, },
+    { -1, NULL, NULL, },
+};
+
+/* Misc tests */
+static tests_t tests_m[] = {
+#if 1
+    /* Integer rotate: TODO */
+    { 0x0001, "clrlwi 1", &test_clrlwi1, },
+    { 0x0001, "clrlwi 2", &test_clrlwi2, },
+    { 0x0001, "clrlwi 3", &test_clrlwi3, },
+    { 0x0001, "clrlwi 4", &test_clrlwi4, },
+    { 0x0001, "clrlwi. 1", &test_clrlwi_1, },
+    { 0x0001, "clrlwi. 2", &test_clrlwi_2, },
+    { 0x0001, "clrlwi. 3", &test_clrlwi_3, },
+    { 0x0001, "clrlwi. 4", &test_clrlwi_4, },
+    { 0x0001, "clrlslwi 1", &test_clrlslwi1, },
+    { 0x0001, "clrlslwi 2", &test_clrlslwi2, },
+    { 0x0001, "clrlslwi 3", &test_clrlslwi3, },
+    { 0x0001, "clrlslwi 4", &test_clrlslwi4, },
+    { 0x0001, "clrlslwi 5", &test_clrlslwi5, },
+    { 0x0001, "clrlslwi 6", &test_clrlslwi6, },
+    { 0x0001, "clrlslwi 7", &test_clrlslwi7, },
+    { 0x0001, "clrlslwi. 1", &test_clrlslwi_1, },
+    { 0x0001, "clrlslwi. 2", &test_clrlslwi_2, },
+    { 0x0001, "clrlslwi. 3", &test_clrlslwi_3, },
+    { 0x0001, "clrlslwi. 4", &test_clrlslwi_4, },
+    { 0x0001, "clrlslwi. 5", &test_clrlslwi_5, },
+    { 0x0001, "clrlslwi. 6", &test_clrlslwi_6, },
+    { 0x0001, "clrlslwi. 7", &test_clrlslwi_7, },
+    { 0x0001, "clrrwi", &test_clrrwi, },
+    { 0x0001, "clrrwi.", &test_clrrwi_, },
+    { 0x0001, "extlwi", &test_extlwi, },
+    { 0x0001, "extlwi.", &test_extlwi_, },
+    { 0x0001, "extrwi", &test_extrwi, },
+    { 0x0001, "extrwi.", &test_extrwi_, },
+    { 0x0001, "rotlwi", &test_rotlwi, },
+    { 0x0001, "rotlwi.", &test_rotlwi_, },
+    { 0x0001, "rotrwi", &test_rotrwi, },
+    { 0x0001, "rotrwi.", &test_rotrwi_, },
+    { 0x0001, "slwi", &test_slwi, },
+    { 0x0001, "slwi.", &test_slwi_, },
+    { 0x0001, "srwi", &test_srwi, },
+    { 0x0001, "srwi.", &test_srwi_, },
+    { 0x0002, "rlwnm 0, 15", &test_rlwnm0, },
+    { 0x0002, "rlwnm. 0, 15", &test_rlwnm0_, },
+    { 0x0002, "rlwnm 16, 31", &test_rlwnm16, },
+    { 0x0002, "rlwnm. 16, 31", &test_rlwnm16_, },
+    /* Integer rotate: TODO */
+    { 0x0001, "clrlwi 1 2", &test_clrlwi1_2, },
+    { 0x0001, "clrlwi 2 2", &test_clrlwi2_2, },
+    { 0x0001, "clrlwi 3 2", &test_clrlwi3_2, },
+    { 0x0001, "clrlwi 4 2", &test_clrlwi4_2, },
+    { 0x0001, "clrlwi. 1 2", &test_clrlwi_1_2, },
+    { 0x0001, "clrlwi. 2 2", &test_clrlwi_2_2, },
+    { 0x0001, "clrlwi. 3 2", &test_clrlwi_3_2, },
+    { 0x0001, "clrlwi. 4 2", &test_clrlwi_4_2, },
+    { 0x0001, "clrlslwi 1 2", &test_clrlslwi1_2, },
+    { 0x0001, "clrlslwi 2 2", &test_clrlslwi2_2, },
+    { 0x0001, "clrlslwi 3 2", &test_clrlslwi3_2, },
+    { 0x0001, "clrlslwi 4 2", &test_clrlslwi4_2, },
+    { 0x0001, "clrlslwi 5 2", &test_clrlslwi5_2, },
+    { 0x0001, "clrlslwi 6 2", &test_clrlslwi6_2, },
+    { 0x0001, "clrlslwi 7 2", &test_clrlslwi7_2, },
+    { 0x0001, "clrlslwi. 1 2", &test_clrlslwi_1_2, },
+    { 0x0001, "clrlslwi. 2 2", &test_clrlslwi_2_2, },
+    { 0x0001, "clrlslwi. 3 2", &test_clrlslwi_3_2, },
+    { 0x0001, "clrlslwi. 4 2", &test_clrlslwi_4_2, },
+    { 0x0001, "clrlslwi. 5 2", &test_clrlslwi_5_2, },
+    { 0x0001, "clrlslwi. 6 2", &test_clrlslwi_6_2, },
+    { 0x0001, "clrlslwi. 7 2", &test_clrlslwi_7_2, },
+    { 0x0001, "clrrwi 2", &test_clrrwi_2, },
+    { 0x0001, "clrrwi. 2", &test_clrrwi__2, },
+    { 0x0001, "extlwi 2", &test_extlwi_2, },
+    { 0x0001, "extlwi. 2", &test_extlwi__2, },
+    { 0x0001, "extrwi 2", &test_extrwi_2, },
+    { 0x0001, "extrwi. 2", &test_extrwi__2, },
+    { 0x0001, "rotlwi 2", &test_rotlwi_2, },
+    { 0x0001, "rotlwi. 2", &test_rotlwi__2, },
+    { 0x0001, "rotrwi 2", &test_rotrwi_2, },
+    { 0x0001, "rotrwi. 2", &test_rotrwi__2, },
+    { 0x0001, "slwi 2", &test_slwi_2, },
+    { 0x0001, "slwi. 2", &test_slwi__2, },
+    { 0x0001, "srwi 2", &test_srwi_2, },
+    { 0x0001, "srwi. 2", &test_srwi__2, },
+    { 0x0002, "rlwnm 0, 15 2", &test_rlwnm0_2, },
+    { 0x0002, "rlwnm. 0, 15 2", &test_rlwnm0__2, },
+    { 0x0002, "rlwnm 16, 31 2", &test_rlwnm16_2, },
+    { 0x0002, "rlwnm. 16, 31 2", &test_rlwnm16__2, },
+#endif
+    { 0x0001, "rlwinm 1", &test_rlwinm1, },
+    { 0x0001, "rlwinm 2", &test_rlwinm2, },
+    { 0x0001, "rlwinm 3", &test_rlwinm3, },
+    { 0x0001, "rlwinm 4", &test_rlwinm4, },
+    { 0x0001, "rlwinm. 1", &test_rlwinm_1, },
+    { 0x0001, "rlwinm. 2", &test_rlwinm_2, },
+    { 0x0001, "rlwinm. 3", &test_rlwinm_3, },
+    { 0x0001, "rlwinm. 4", &test_rlwinm_4, },
+    { -1, NULL, NULL, },
+};
+
+#if 0
+    { 0x0002 | FL_MEM, "lbzx", &test_lbzx, },
+    { 0x0002 | FL_MEM, "lbzux", &test_lbzux, },
+    { 0x0002 | FL_MEM, "lhax", &test_lhzx, },
+    { 0x0002 | FL_MEM, "lhaux", &test_lhzux, },
+    { 0x0002 | FL_MEM, "lhzx", &test_lhzx, },
+    { 0x0002 | FL_MEM, "lhzux", &test_lhzux, },
+    { 0x0002 | FL_MEM, "lwzx", &test_lwzx, },
+    { 0x0002 | FL_MEM, "lwzux", &test_lwzux, },
+    { 0x0003 | FL_MEM, "stbx", &test_stb, },
+    { 0x0003 | FL_MEM, "stbux", &test_stbu, },
+    { 0x0003 | FL_MEM, "sthx", &test_sth, },
+    { 0x0003 | FL_MEM, "sthux", &test_sthu, },
+    { 0x0003 | FL_MEM, "stwx", &test_stw, },
+    { 0x0003 | FL_MEM, "stwux", &test_sthw, },
+#endif
+
+static unsigned long operands[] = {
+    0x00000000,
+    0x00000001,
+    0x0000000f,
+    0x00000010,
+    0x0000001f,
+    0x00000020,
+    0x00000064,
+    0x0000006f,
+    0x0000007f,
+    0x00000080,
+    0x000000ff,
+    0x00000100,
+    0x00007fff,
+    0x00008000,
+    0x0000ffff,
+    0x00010000,
+    0x007fffff,
+    0x00800000,
+    0x00ffffff,
+    0x01000000,
+    0x7fffffff,
+    0x80000000,
+    0xffffffff,
+};
+
+static unsigned long ops16[] = {
+    0x00000000,
+    0x00000001,
+    0x0000000f,
+    0x00000010,
+    0x0000001f,
+    0x00000020,
+    0x0000002f,
+    0x0000003f,
+    0x0000007f,
+    0x00000080,
+    0x000000ff,
+    0x00000100,
+    0x00000101,
+    0x000003ff,
+    0x000007ff,
+    0x00000800,
+    0x00000fff,
+    0x00001000,
+    0x00003fff,
+    0x00007fff,
+    0x0000ffff,
+};
+
+unsigned long testbuf[2];
+static int do_test (int fd, tests_t *test_table)
+{
+    test_t test = NULL;
+    unsigned long keep;
+    int i, j, k, l, xer = 0;
+
+change_xer:
+    for (i = 0; test_table[i].test != NULL; i++) {
+        outstr(fd, test_mess, strlen(test_mess));
+        outstr(fd, "test: ", 6);
+        outstr(fd, test_table[i].name, strlen(test_table[i].name));
+        outstr(fd, "\n", 1);
+        switch (test_table[i].flags & FL_NR) {
+        case 0:
+            outstr(fd, test_table[i].name, strlen(test_table[i].name));
+            outstr(fd, " ", 1);
+            outstr(fd, "\n", 1);
+            init_ppc(xer);
+            dump_ppc_state(fd);
+            test = test_table[i].test;
+            init_ppc(xer);
+            (*test)();
+            dump_ppc_state(fd);
+            break;
+        case 1:
+            for (j = 0;; j++) {
+                outstr(fd, test_table[i].name, strlen(test_table[i].name));
+                outstr(fd, " 0x", 3);
+                outhex(fd, operands[j]);
+                outstr(fd, "\n", 1);
+                init_ppc(xer);
+                r16 = operands[j];
+                dump_ppc_state(fd);
+                init_ppc(xer);
+                test = test_table[i].test;
+                r16 = operands[j];
+                (*test)();
+                dump_ppc_state(fd);
+                if (operands[j] == 0xffffffff)
+                    break;
+                outstr(fd, sep_mess, strlen(sep_mess));
+            }
+            break;
+        case 2:
+            for (j = 0;; j++) {
+                for (k = 0;; k++) {
+                    outstr(fd, test_table[i].name, strlen(test_table[i].name));
+                    outstr(fd, " 0x", 3);
+                    outhex(fd, operands[j]);
+                    outstr(fd, ", 0x", 4);
+                    if ((test_table[i].flags & FL_IMM16) != 0) {
+                        outhex(fd, ops16[k]);
+                    } else {
+                        outhex(fd, operands[k]);
+                    }
+                    outstr(fd, "\n", 1);
+                    if ((test_table[i].flags & FL_IMM16) != 0) {
+                        patch_imm16(testbuf, test_table[i].test, ops16[k]);
+                        test = (void *)testbuf;
+                        flush_icache(test);
+                        keep = 0;
+                    } else {
+                        test = test_table[i].test;
+                        keep = operands[k];
+                    }
+                    init_ppc(xer);
+                    r16 = operands[j];
+                    r17 = keep;
+                    dump_ppc_state(fd);
+                    init_ppc(xer);
+                    r16 = operands[j];
+                    r17 = keep;
+                    (*test)();
+                    dump_ppc_state(fd);
+                    if (operands[k] == 0xffffffff)
+                        break;
+                    outstr(fd, sep_mess, strlen(sep_mess));
+                }
+                if (operands[j] == 0xffffffff)
+                    break;
+                outstr(fd, sep_mess, strlen(sep_mess));
+            }
+            break;
+        case 3:
+            for (j = 0;; j++) {
+                for (k = 0;; k++) {
+                    for (l = 0;; l++) {
+                        outstr(fd, test_table[i].name,
+                               strlen(test_table[i].name));
+                        outstr(fd, " 0x", 3);
+                        outhex(fd, operands[j]);
+                        outstr(fd, ", 0x", 4);
+                        outhex(fd, operands[k]);
+                        outstr(fd, ", 0x", 4);
+                        if ((test_table[i].flags & FL_IMM16) != 0) {
+                            outhex(fd, ops16[l]);
+                        } else {
+                            outhex(fd, operands[l]);
+                        }
+                        outstr(fd, "\n", 1);
+                        init_ppc(xer);
+                        r16 = operands[j];
+                        r17 = operands[k];
+                        keep = 0;
+                        if ((test_table[i].flags & FL_IMM16) != 0) {
+                            testbuf[0] = *((unsigned long *)test + 0);
+                            patch_imm16(testbuf, test_table[i].test, ops16[l]);
+                            test = (void *)testbuf;
+                            flush_icache(test);
+                            keep = 0;
+                        } else {
+                            test = test_table[i].test;
+                            keep = operands[k];
+                        }
+                        r18 = keep;
+                        dump_ppc_state(fd);
+                        init_ppc(xer);
+                        r16 = operands[j];
+                        r17 = operands[k];
+                        r18 = keep;
+                        outstr(fd, "test\n", 5);
+                        (*test)();
+                        dump_ppc_state(fd);
+                        if (operands[l] == 0xffffffff)
+                            break;
+                        outstr(fd, sep_mess, strlen(sep_mess));
+                    }
+                    if (operands[k] == 0xffffffff)
+                        break;
+                    outstr(fd, sep_mess, strlen(sep_mess));
+                }
+                if (operands[j] == 0xffffffff)
+                    break;
+                outstr(fd, sep_mess, strlen(sep_mess));
+            }
+            break;
+        default:
+            outstr(fd, error_mess, strlen(error_mess));
+            return -1;
+        }
+    }
+    if (++xer < 4)
+        goto change_xer;
+    
+    return 0;
+}
+
+static void dump_env (int fd, int argc, char *const *argv, char *const *envp)
+{
+    unsigned long sp, *cur;
+    int i, j;
+
+    __asm__ __volatile__ ("mr %0, 1" : "=r"(sp));
+    /* Dump stack, argv and envp pointers */
+    outstr(fd, "Stack: ", strlen("Stack: "));
+    outhex(fd, sp);
+    outstr(fd, " ", 1);
+    outhex(fd, (unsigned long)__sp);
+    outstr(fd, "\n", 1);
+    fsync(fd);
+    cur = __sp - 32;
+    for (i = 0; ((unsigned long)cur & 0xfff) != 0; i++) {
+        outhex(fd, (unsigned long)cur);
+        outstr(fd, ": ", 2);
+        for (j = 0; j < 4; j++) {
+            outhex(fd, *cur++);
+            outstr(fd, " ", 1);
+        }
+        outstr(fd, "\n", 1);
+    }
+    outstr(fd, " argv: ", strlen(" argv: "));
+    outhex(fd, (unsigned long)argv);
+    outstr(fd, " envp: ", strlen(" envp: "));
+    outhex(fd, (unsigned long)envp);
+    outstr(fd, "\n", 1);
+    /* Dump args and environment */
+    outhex(fd, argc);
+    outstr(fd, " args\n", strlen(" args\n"));
+#if 1
+    for (i = 0; i < argc; i++) {
+        outstr(fd, " arg ", 5);
+        outhex(fd, i);
+        outstr(fd, " : ", 3);
+        outhex(fd, (unsigned long)argv[i]);
+        outstr(fd, " : ", 3);
+        outstr(fd, argv[i], strlen(argv[i]));
+        outstr(fd, "\n", 1);
+    }
+#endif
+    outstr(fd, "Env\n", strlen("Env\n"));
+    for (i = 0; envp[i] != NULL; i++) {
+        outstr(fd, "envstr ", 4);
+        outhex(fd, i);
+        outstr(fd, " : ", 3);
+        outhex(fd, (unsigned long)envp[i]);
+        outstr(fd, " : ", 3);
+        outstr(fd, envp[i], strlen(envp[i]));
+        outstr(fd, "\n", 1);
+    }
+}
+
+int main (int argc, char **argv, char **envp)
+{
+    int logfile;
+
+    unlink(logfname);
+    logfile = open(logfname, O_WRONLY | O_CREAT, 0644);
+    if (logfile < 0)
+        return 1;
+    sync();
+    outstr(logfile, first_mess, strlen(first_mess));
+    fsync(logfile);
+#if 0
+    dump_env(logfile, argc, argv, envp);
+#endif
+    if (do_test(logfile, tests_1a) < 0) {
+        outstr(logfile, test1_err, strlen(test1_err));
+        outstr(logfile, part1_err, strlen(part1_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_1b) < 0) {
+        outstr(logfile, test1_err, strlen(test1_err));
+        outstr(logfile, part2_err, strlen(part2_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_2a) < 0) {
+        outstr(logfile, test2_err, strlen(test2_err));
+        outstr(logfile, part1_err, strlen(part1_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_2b) < 0) {
+        outstr(logfile, test2_err, strlen(test2_err));
+        outstr(logfile, part2_err, strlen(part2_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_2c) < 0) {
+        outstr(logfile, test2_err, strlen(test2_err));
+        outstr(logfile, part3_err, strlen(part3_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_2d) < 0) {
+        outstr(logfile, test2_err, strlen(test2_err));
+        outstr(logfile, part4_err, strlen(part4_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_ia) < 0) {
+        outstr(logfile, testi_err, strlen(testi_err));
+        outstr(logfile, part1_err, strlen(part1_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_ib) < 0) {
+        outstr(logfile, testi_err, strlen(testi_err));
+        outstr(logfile, part2_err, strlen(part2_err));
+        goto out;
+    }
+    if (do_test(logfile, tests_m) < 0) {
+        outstr(logfile, test1_err, strlen(test1_err));
+        goto out;
+    }
+ out:
+    close(logfile);
+
+    return 0;
+}
+
+void _start (void)
+{
+    register unsigned long __spp  __asm__ ("r1");
+    unsigned long *cur;
+    unsigned long *__argv, *__envp, __argc;
+    int __status, i;
+    
+    __sp = (unsigned long *)*((unsigned long *)__spp);
+    cur = __sp;
+    __argc = *cur;
+    __argv = cur + 1;
+    __envp = cur + 2 + __argc;
+    /* Linux is *STILL* buggy and doesn't respect the API */
+    if (*__argv == 0) {
+        unsigned long tmp = *__envp;
+
+        while (*(unsigned long *)tmp != 0)
+            tmp--;
+        tmp += 4;
+        for (i = 0; i < __argc; i++) {
+            __argv[i] = (unsigned long)tmp;
+            while (*(unsigned char *)tmp)
+                tmp++;
+            tmp++;
+        }
+    }
+    __status = main(__argc, (char **)__argv, (char **)__envp);
+    exit(__status);
+}