From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by monty-python.gnu.org with tmda-scanned (Exim 4.34) id 1BT9VT-0007pe-7D for qemu-devel@nongnu.org; Wed, 26 May 2004 21:16:27 -0400 Received: from mail by monty-python.gnu.org with spam-scanned (Exim 4.34) id 1BT9Rr-0007XX-D0 for qemu-devel@nongnu.org; Wed, 26 May 2004 21:13:14 -0400 Received: from [213.146.130.142] (helo=trantor.org.uk) by monty-python.gnu.org with esmtp (TLSv1:DES-CBC3-SHA:168) (Exim 4.34) id 1BT9Ow-0007BT-Tn for qemu-devel@nongnu.org; Wed, 26 May 2004 21:09:43 -0400 Subject: Re: [Qemu-devel] PCI: Memory mapped / ROM resources From: Gianni Tedesco In-Reply-To: <40B51F4D.8000307@bellard.org> References: <1085582014.20025.11.camel@sherbert> <40B4FC37.7080601@bellard.org> <1085603535.4321.8.camel@sherbert> <40B51F4D.8000307@bellard.org> Content-Type: text/plain Message-Id: <1085620206.4321.19.camel@sherbert> Mime-Version: 1.0 Date: Thu, 27 May 2004 02:10:07 +0100 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Wed, 2004-05-26 at 23:50, Fabrice Bellard wrote: > Gianni Tedesco wrote: > > > I'm adding a host PCI proxy layer that works under Linux, ie: make host > > PCI devices appear within the emulator. Similar to 'pcidev' on bochs, > > but without a custom kernel module, and some minor performance > > enhancements. I ought to have a patch ready by tomorrow evening. > > Interesting. How do you redirect irqs ? A small patch to /proc/pci which adds an ioctl PCIIOC_SIGIRQ which allows for the kernel to send (user defined) rtsignals when IRQs are recieved. It may be interesting to X folk and the like, so with some cleanups maybe they'll merge it, who knows. > > PS. I am using mmap() on /proc/pci/bus/XX/YY.Z nodes to map PCI > > registers, probably there is a nice way to allow the code generator to > > generate accesses directly on to these vmas? It's probably not that much > > of a win in any case, but interesting. > > You'd better defines memory access callbacks. It could be possible to > define RAM memory areas for which the access is optimised internally by > the CPU core, but currently they must stay in the phys_ram_base array. It will be OK if i pass mmap a start address and map right over some regions in phys_ram_base? -- // Gianni Tedesco (gianni at scaramanga dot co dot uk) lynx --source www.scaramanga.co.uk/scaramanga.asc | gpg --import 8646BE7D: 6D9F 2287 870E A2C9 8F60 3A3C 91B5 7669 8646 BE7D