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From: Ye Wen <wen@umail.ucsb.edu>
To: qemu-devel@nongnu.org
Subject: Another related question Re: [Qemu-devel] Question about softmmu
Date: Sun,  7 Nov 2004 16:32:45 -0800	[thread overview]
Message-ID: <1099873965.418ebead76c07@webaccess.umail.ucsb.edu> (raw)
In-Reply-To: <1099788719.418d71af8a4f1@webmail.u-picardie.fr>

Thanks Olivier.

Another question:
When translating instructions that access PC, e.g. move pc to register,
actually the PC value at translation time is used. This causes a problem
that if the address mapping changes later, this translated basic block
is still using the old PC value. Is it right? How does QEMU deal with it?
Or is it completely impossible?

Thanks,
Ye

Quoting olivier cozette <olivier.cozette@u-picardie.fr>:

> Hello,
>
> >I'm reading the QEMU code. I have a question haunting my mind for some time
> >about tb flushing due to MMU change. Generally, whenever the page table has
> >any change, we should flush the tb hash table. But I only see in the code
> that
> >when CR3 is changed, the tb_flush is called. What if the CR3 does not
> change,
> >but some level 2 page table in the memory change, should the tb also be
> >flushed?
>
>
> In this case, in the real processor (see Intel Manual), the processor TLBs
> (it's
> like the Qemu tb) are not flushed, so Qemu act as a real processor.
>
> Olivier
>
>
> _______________________________________________
> Qemu-devel mailing list
> Qemu-devel@nongnu.org
> http://lists.nongnu.org/mailman/listinfo/qemu-devel
>


--
Ye Wen
wen@umail.ucsb.edu

      reply	other threads:[~2004-11-08  0:41 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-11-07  0:51 [Qemu-devel] Question about softmmu olivier cozette
2004-11-08  0:32 ` Ye Wen [this message]

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