From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CQxbX-0006m3-FF for qemu-devel@nongnu.org; Sun, 07 Nov 2004 19:41:55 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1CQxbW-0006ld-Kq for qemu-devel@nongnu.org; Sun, 07 Nov 2004 19:41:55 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CQxbW-0006la-Iv for qemu-devel@nongnu.org; Sun, 07 Nov 2004 19:41:54 -0500 Received: from [128.111.151.219] (helo=sakall.umail.ucsb.edu) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CQxSg-0005uA-MU for qemu-devel@nongnu.org; Sun, 07 Nov 2004 19:32:46 -0500 Received: from page.umail.ucsb.edu ([128.111.151.221] helo=localhost) by sakall.umail.ucsb.edu with esmtp (Exim 4.34) id 1CQxSf-0002I7-AT for qemu-devel@nongnu.org; Sun, 07 Nov 2004 16:32:45 -0800 Message-ID: <1099873965.418ebead76c07@webaccess.umail.ucsb.edu> Date: Sun, 7 Nov 2004 16:32:45 -0800 From: Ye Wen Subject: Another related question Re: [Qemu-devel] Question about softmmu References: <1099788719.418d71af8a4f1@webmail.u-picardie.fr> In-Reply-To: <1099788719.418d71af8a4f1@webmail.u-picardie.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Thanks Olivier. Another question: When translating instructions that access PC, e.g. move pc to register, actually the PC value at translation time is used. This causes a problem that if the address mapping changes later, this translated basic block is still using the old PC value. Is it right? How does QEMU deal with it? Or is it completely impossible? Thanks, Ye Quoting olivier cozette : > Hello, > > >I'm reading the QEMU code. I have a question haunting my mind for some time > >about tb flushing due to MMU change. Generally, whenever the page table has > >any change, we should flush the tb hash table. But I only see in the code > that > >when CR3 is changed, the tb_flush is called. What if the CR3 does not > change, > >but some level 2 page table in the memory change, should the tb also be > >flushed? > > > In this case, in the real processor (see Intel Manual), the processor TLBs > (it's > like the Qemu tb) are not flushed, so Qemu act as a real processor. > > Olivier > > > _______________________________________________ > Qemu-devel mailing list > Qemu-devel@nongnu.org > http://lists.nongnu.org/mailman/listinfo/qemu-devel > -- Ye Wen wen@umail.ucsb.edu