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([2001:8003:c020:6900:324d:cbc2:5f8b:3a9d]) by smtp.gmail.com with ESMTPSA id e27-20020a056a0000db00b006d9bf71461asm7105954pfj.86.2023.12.28.15.33.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Dec 2023 15:33:51 -0800 (PST) Message-ID: <10c1404a-dff6-4f1e-95f6-9273d4e53c75@linaro.org> Date: Fri, 29 Dec 2023 10:33:44 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] target/riscv: Add pointer masking tb flags Content-Language: en-US To: Alexey Baturo Cc: zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20231224044812.2072140-1-me@deliversmonkey.space> <20231224044812.2072140-5-me@deliversmonkey.space> From: Richard Henderson In-Reply-To: <20231224044812.2072140-5-me@deliversmonkey.space> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/24/23 15:48, Alexey Baturo wrote: > From: Alexey Baturo > > Signed-off-by: Alexey Baturo > --- > target/riscv/cpu.h | 15 +++++++++------ > target/riscv/cpu_helper.c | 3 +++ > target/riscv/translate.c | 5 +++++ > 3 files changed, 17 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c607a94bba..038b86db4b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -538,14 +538,17 @@ FIELD(TB_FLAGS, VILL, 14, 1) > FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) > /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ > FIELD(TB_FLAGS, XL, 16, 2) > -FIELD(TB_FLAGS, VTA, 18, 1) > -FIELD(TB_FLAGS, VMA, 19, 1) > +/* If pointer masking should be applied and address sign extended */ > +FIELD(TB_FLAGS, PM_PMM, 18, 2) > +FIELD(TB_FLAGS, PM_SIGNEXTEND, 20, 1) > +FIELD(TB_FLAGS, VTA, 21, 1) > +FIELD(TB_FLAGS, VMA, 22, 1) > /* Native debug itrigger */ > -FIELD(TB_FLAGS, ITRIGGER, 20, 1) > +FIELD(TB_FLAGS, ITRIGGER, 23, 1) > /* Virtual mode enabled */ > -FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) > -FIELD(TB_FLAGS, PRIV, 22, 2) > -FIELD(TB_FLAGS, AXL, 24, 2) > +FIELD(TB_FLAGS, VIRT_ENABLED, 24, 1) > +FIELD(TB_FLAGS, PRIV, 25, 2) > +FIELD(TB_FLAGS, AXL, 27, 2) Any particular reason to add these in the middle? Something to consider as a somewhat unrelated cleanup would be to add an eighth MMUIdx for MMUIdx_M + no translation. This would be used both for MBARE and internally within get_physical_address for accessing PTEs. See also the ptw_translate cleanups in target/i386 for atomic PTE updates (4a1e9d4d11cd). At which point PM_SIGNEXTEND can be replaced by a test vs mmu_idx, saving a bit in tb_flags. Something for later, anyway. r~