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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c68sm9188740pfc.156.2020.02.27.19.33.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2020 19:33:43 -0800 (PST) Subject: Re: [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com References: <20200225103508.7651-1-zhiwei_liu@c-sky.com> <20200225103508.7651-2-zhiwei_liu@c-sky.com> <4cfb56d6-34a5-0e35-87a0-2aefaafa4221@linaro.org> <287bde05-421c-f49c-2404-fdee183c9e12@c-sky.com> From: Richard Henderson Message-ID: <10e50ea8-7614-f094-a827-38ed09462f29@linaro.org> Date: Thu, 27 Feb 2020 19:33:41 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <287bde05-421c-f49c-2404-fdee183c9e12@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, linux-csky@vger.kernel.org, wxy194768@alibaba-inc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/27/20 5:50 PM, LIU Zhiwei wrote: >> This is not what I had in mind, and looks wrong as well. >> >> int idx = (index * mlen) / 64; >> int pos = (index * mlen) % 64; >> return (((uint64_t *)v0)[idx] >> pos) & 1; >> >> You also might consider passing log2(mlen), so the multiplication could be >> strength-reduced to a shift. > I don't think so. For example, when mlen is 8 bits and index is 0, it will > reduce to > > return (((uint64_t *)v0)[0]) & 1 > > And it's not right. > > The right bit is first bit in vector register 0. And in host big endianess, > it will beĀ  the first bit of the seventh byte. You've forgotten that we've just done an 8-byte big-endian load, which means that we *are* looking at the first bit of the byte at offset 7. It is right. >> You don't need to pass mlen, since it's > Yes. I finally remembered all of the bits that go into mlen and thought I had deleted that sentence -- apparently I only removed half. ;-) r~