qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Ye Wen <wen@umail.ucsb.edu>
To: qemu-devel@nongnu.org
Subject: Re:Another related question Re: [Qemu-devel] Question about softmmu
Date: Tue,  9 Nov 2004 11:33:00 -0800	[thread overview]
Message-ID: <1100028780.41911b6c1c3cf@webaccess.umail.ucsb.edu> (raw)
In-Reply-To: <006401c4c675$556b86c0$f618100a@Olivier>

Thanks for your reply, Olivier.

So EIP is just the offset of current instruction. When address mapping changes,
the CS segment register also changes. That's why QEMU does not need to flush
the code. Am I right?

The reason I'm thinking about this is because I'm implementing QEMU's
translation method in my ARM simulator which needs to simulate the whole system
running Linux. In ARM, since PC is just r15, you can access it as a normal
register and it is the absolute virtual address. So I wonder if I have to flush
code cache every time page table changes.

Thanks,
Ye
Quoting Olivier Cozette <olivier.cozette@u-picardie.fr>:

>
>   Hello Ye,
>
> First, I will describe the memory access. All access to memory from the CPU,
> data access or load instruction access cross the TLB (Translation Look aside
> Buffer), the TLB convert the virtual address to the real address (it's a
> cache of the page mapping), so only the real address go to the memory
> subsystem or the cache. Note that the TLB are only flushed when you change
> CR3 value or if you use INVLPG instruction.
>
>
> -------
> | Proc|
> ------->=====>-------------
>               |  TLB      |
>               ------------->=======\/
> 						--------------
>                                    | Cache/Memory|
>                                    ---------------
>
> With i386, the only to get the pc (eip register) is to use the CALL
> instruction, this instruction store the virtual next PC (eip) and so if the
> mapping change, the next PC change.
>
> With Qemu in target-i386/translate.c you have this code :
>
>     case 2: /* call Ev */
>             /* XXX: optimize if memory (no 'and' is necessary) */
>             if (s->dflag == 0)
>                 gen_op_andl_T0_ffff();
>             next_eip = s->pc - s->cs_base;
>             gen_op_movl_T1_im(next_eip);
>             gen_push_T1(s);
>             gen_op_jmp_T0();
>             gen_eob(s);
>             break;
>
>
>
>
> Olivier
>
>
>
> _______________________________________________
> Qemu-devel mailing list
> Qemu-devel@nongnu.org
> http://lists.nongnu.org/mailman/listinfo/qemu-devel
>


--
Ye Wen
wen@umail.ucsb.edu

  reply	other threads:[~2004-11-09 19:41 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-11-09 16:01 Re:Another related question Re: [Qemu-devel] Question about softmmu Olivier Cozette
2004-11-09 19:33 ` Ye Wen [this message]
  -- strict thread matches above, loose matches on Subject: below --
2004-11-10 14:15 olivier cozette
2004-11-11  8:21 ` Ye Wen
2004-11-12 17:30   ` RE : Another " Olivier Cozette
2004-11-10 14:15 olivier cozette

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1100028780.41911b6c1c3cf@webaccess.umail.ucsb.edu \
    --to=wen@umail.ucsb.edu \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).