From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CRbsA-0002yz-8o for qemu-devel@nongnu.org; Tue, 09 Nov 2004 14:41:46 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1CRbs9-0002yQ-Gf for qemu-devel@nongnu.org; Tue, 09 Nov 2004 14:41:45 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CRbs8-0002yA-GJ for qemu-devel@nongnu.org; Tue, 09 Nov 2004 14:41:45 -0500 Received: from [128.111.151.220] (helo=lebeau.umail.ucsb.edu) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CRbjh-0005Tq-53 for qemu-devel@nongnu.org; Tue, 09 Nov 2004 14:33:01 -0500 Received: from page.umail.ucsb.edu ([128.111.151.221] helo=localhost) by lebeau.umail.ucsb.edu with esmtp (Exim 4.34) id 1CRbjf-000Ato-Ul for qemu-devel@nongnu.org; Tue, 09 Nov 2004 11:32:59 -0800 Message-ID: <1100028780.41911b6c1c3cf@webaccess.umail.ucsb.edu> Date: Tue, 9 Nov 2004 11:33:00 -0800 From: Ye Wen Subject: Re:Another related question Re: [Qemu-devel] Question about softmmu References: <006401c4c675$556b86c0$f618100a@Olivier> In-Reply-To: <006401c4c675$556b86c0$f618100a@Olivier> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Thanks for your reply, Olivier. So EIP is just the offset of current instruction. When address mapping changes, the CS segment register also changes. That's why QEMU does not need to flush the code. Am I right? The reason I'm thinking about this is because I'm implementing QEMU's translation method in my ARM simulator which needs to simulate the whole system running Linux. In ARM, since PC is just r15, you can access it as a normal register and it is the absolute virtual address. So I wonder if I have to flush code cache every time page table changes. Thanks, Ye Quoting Olivier Cozette : > > Hello Ye, > > First, I will describe the memory access. All access to memory from the CPU, > data access or load instruction access cross the TLB (Translation Look aside > Buffer), the TLB convert the virtual address to the real address (it's a > cache of the page mapping), so only the real address go to the memory > subsystem or the cache. Note that the TLB are only flushed when you change > CR3 value or if you use INVLPG instruction. > > > ------- > | Proc| > ------->=====>------------- > | TLB | > ------------->=======\/ > -------------- > | Cache/Memory| > --------------- > > With i386, the only to get the pc (eip register) is to use the CALL > instruction, this instruction store the virtual next PC (eip) and so if the > mapping change, the next PC change. > > With Qemu in target-i386/translate.c you have this code : > > case 2: /* call Ev */ > /* XXX: optimize if memory (no 'and' is necessary) */ > if (s->dflag == 0) > gen_op_andl_T0_ffff(); > next_eip = s->pc - s->cs_base; > gen_op_movl_T1_im(next_eip); > gen_push_T1(s); > gen_op_jmp_T0(); > gen_eob(s); > break; > > > > > Olivier > > > > _______________________________________________ > Qemu-devel mailing list > Qemu-devel@nongnu.org > http://lists.nongnu.org/mailman/listinfo/qemu-devel > -- Ye Wen wen@umail.ucsb.edu