From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DY9xb-0001c2-AL for qemu-devel@nongnu.org; Tue, 17 May 2005 17:50:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DY9wo-0001Bn-EM for qemu-devel@nongnu.org; Tue, 17 May 2005 17:49:57 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DY9wm-0001Ag-Hm for qemu-devel@nongnu.org; Tue, 17 May 2005 17:49:52 -0400 Received: from [62.210.158.41] (helo=moscou.magic.fr) by monty-python.gnu.org with esmtp (Exim 4.34) id 1DY9Sz-0005if-5v for qemu-devel@nongnu.org; Tue, 17 May 2005 17:19:06 -0400 Subject: Re: [Qemu-devel] [Patch] target-ppc mtcrf instruction not recognized From: "J. Mayer" In-Reply-To: <1116230086.5095.107.camel@gaston> References: <1A902C2A-9E03-42FB-BBFC-B84AA84A5A3E@free.fr> <1116094547.12010.73.camel@rapid> <4920FD1A-05D0-4A7C-BCE6-58036B198978@free.fr> <1116158429.12010.80.camel@rapid> <1116230086.5095.107.camel@gaston> Content-Type: text/plain Date: Tue, 17 May 2005 23:10:52 +0200 Message-Id: <1116364252.15980.50.camel@rapid> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, 2005-05-16 at 17:54 +1000, Benjamin Herrenschmidt wrote: > > OK, I did put this in my working repository and I'll submit this to > > Fabrice. > > Please try to do this change to check if other bits need to be relax or > > not: > > > > Index: target-ppc/translate.c > > =================================================================== > > RCS file: /cvsroot/qemu/qemu/target-ppc/translate.c,v > > retrieving revision 1.31 > > diff -u -r1.31 translate.c > > --- target-ppc/translate.c 12 May 2005 18:46:11 -0000 1.31 > > +++ target-ppc/translate.c 14 May 2005 17:14:35 -0000 > > @@ -2123,7 +2123,7 @@ > > } > > > > /* mtcrf */ > > -GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC) > > +GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) > > { > > gen_op_load_gpr_T0(rS(ctx->opcode)); > > gen_op_store_cr(CRM(ctx->opcode)); > > > > And maybe someone should fill an Apple bug report to tell them their as > > is buggy ;-) > > It is definitely a bug in Apple assembler I would say, so I suggest you > add a comment in the above patch in order to avoid somebody later on > "fixing" your mask :) Piotr Krysiuk pointed that it's, in fact, a new form of the instruction. A new PowerPC specification has been released in january, adding mtocrf and mfocrf ('o' like optimized). Those new forms only transfer one set of flags (then it's like the previous form when only one bit is set in the control register). The specification also say that "old" form is supported as a micro-coded instruction. Then, I guess new PowerPC do implement this new instruction. But Apple is then supposed to emulate it when running on a PowerPC that does not support it, I guess. I will implement the new form, so it most crf transfers can be optimized. The latest PowerPC specification is to be found here: -- J. Mayer Never organized