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[83.52.54.50]) by smtp.gmail.com with ESMTPSA id g143sm11450301wme.0.2020.09.04.09.01.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Sep 2020 09:01:35 -0700 (PDT) Subject: Re: [PATCH 2/2] target/arm: Remove no-longer-reachable 32-bit KVM code To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200904154156.31943-1-peter.maydell@linaro.org> <20200904154156.31943-3-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Autocrypt: addr=philmd@redhat.com; keydata= mQINBDXML8YBEADXCtUkDBKQvNsQA7sDpw6YLE/1tKHwm24A1au9Hfy/OFmkpzo+MD+dYc+7 bvnqWAeGweq2SDq8zbzFZ1gJBd6+e5v1a/UrTxvwBk51yEkadrpRbi+r2bDpTJwXc/uEtYAB GvsTZMtiQVA4kRID1KCdgLa3zztPLCj5H1VZhqZsiGvXa/nMIlhvacRXdbgllPPJ72cLUkXf z1Zu4AkEKpccZaJspmLWGSzGu6UTZ7UfVeR2Hcc2KI9oZB1qthmZ1+PZyGZ/Dy+z+zklC0xl XIpQPmnfy9+/1hj1LzJ+pe3HzEodtlVA+rdttSvA6nmHKIt8Ul6b/h1DFTmUT1lN1WbAGxmg CH1O26cz5nTrzdjoqC/b8PpZiT0kO5MKKgiu5S4PRIxW2+RA4H9nq7nztNZ1Y39bDpzwE5Sp bDHzd5owmLxMLZAINtCtQuRbSOcMjZlg4zohA9TQP9krGIk+qTR+H4CV22sWldSkVtsoTaA2 qNeSJhfHQY0TyQvFbqRsSNIe2gTDzzEQ8itsmdHHE/yzhcCVvlUzXhAT6pIN0OT+cdsTTfif MIcDboys92auTuJ7U+4jWF1+WUaJ8gDL69ThAsu7mGDBbm80P3vvUZ4fQM14NkxOnuGRrJxO qjWNJ2ZUxgyHAh5TCxMLKWZoL5hpnvx3dF3Ti9HW2dsUUWICSQARAQABtDJQaGlsaXBwZSBN YXRoaWV1LURhdWTDqSAoUGhpbCkgPHBoaWxtZEByZWRoYXQuY29tPokCVQQTAQgAPwIbDwYL CQgHAwIGFQgCCQoLBBYCAwECHgECF4AWIQSJweePYB7obIZ0lcuio/1u3q3A3gUCXsfWwAUJ KtymWgAKCRCio/1u3q3A3ircD/9Vjh3aFNJ3uF3hddeoFg1H038wZr/xi8/rX27M1Vj2j9VH 0B8Olp4KUQw/hyO6kUxqkoojmzRpmzvlpZ0cUiZJo2bQIWnvScyHxFCv33kHe+YEIqoJlaQc JfKYlbCoubz+02E2A6bFD9+BvCY0LBbEj5POwyKGiDMjHKCGuzSuDRbCn0Mz4kCa7nFMF5Jv piC+JemRdiBd6102ThqgIsyGEBXuf1sy0QIVyXgaqr9O2b/0VoXpQId7yY7OJuYYxs7kQoXI 6WzSMpmuXGkmfxOgbc/L6YbzB0JOriX0iRClxu4dEUg8Bs2pNnr6huY2Ft+qb41RzCJvvMyu gS32LfN0bTZ6Qm2A8ayMtUQgnwZDSO23OKgQWZVglGliY3ezHZ6lVwC24Vjkmq/2yBSLakZE 6DZUjZzCW1nvtRK05ebyK6tofRsx8xB8pL/kcBb9nCuh70aLR+5cmE41X4O+MVJbwfP5s/RW 9BFSL3qgXuXso/3XuWTQjJJGgKhB6xXjMmb1J4q/h5IuVV4juv1Fem9sfmyrh+Wi5V1IzKI7 RPJ3KVb937eBgSENk53P0gUorwzUcO+ASEo3Z1cBKkJSPigDbeEjVfXQMzNt0oDRzpQqH2vp apo2jHnidWt8BsckuWZpxcZ9+/9obQ55DyVQHGiTN39hkETy3Emdnz1JVHTU0Q== Message-ID: <11457fd8-725f-5836-e2ef-6c60aee344e5@redhat.com> Date: Fri, 4 Sep 2020 18:01:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200904154156.31943-3-peter.maydell@linaro.org> X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Received-SPF: pass client-ip=207.211.31.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/04 03:58:24 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.107, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/4/20 5:41 PM, Peter Maydell wrote: > Now that 32-bit KVM host support is gone, KVM can never > be enabled unless CONFIG_AARCH64 is true, and some code > paths are no longer reachable and can be deleted. > > Signed-off-by: Peter Maydell > --- [...] > static void arm_max_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > > - if (kvm_enabled()) { > - kvm_arm_set_cpu_features_from_host(cpu); > - } else { > - cortex_a15_initfn(obj); > + cortex_a15_initfn(obj); > > - /* old-style VFP short-vector support */ > - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); > + /* old-style VFP short-vector support */ > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); > > #ifdef CONFIG_USER_ONLY > - /* We don't set these in system emulation mode for the moment, > - * since we don't correctly set (all of) the ID registers to > - * advertise them. > - */ > - set_feature(&cpu->env, ARM_FEATURE_V8); > - { > - uint32_t t; > + /* We don't set these in system emulation mode for the moment, checkpatch might warn "block comment ... separate line" :/ > + * since we don't correctly set (all of) the ID registers to > + * advertise them. > + */ > + set_feature(&cpu->env, ARM_FEATURE_V8); > + { > + uint32_t t; > > - t = cpu->isar.id_isar5; > - t = FIELD_DP32(t, ID_ISAR5, AES, 2); > - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); > - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); > - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); > - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); > - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); > - cpu->isar.id_isar5 = t; > + t = cpu->isar.id_isar5; > + t = FIELD_DP32(t, ID_ISAR5, AES, 2); > + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); > + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); > + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); > + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); > + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); > + cpu->isar.id_isar5 = t; > > - t = cpu->isar.id_isar6; > - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); > - t = FIELD_DP32(t, ID_ISAR6, DP, 1); > - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); > - t = FIELD_DP32(t, ID_ISAR6, SB, 1); > - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); > - cpu->isar.id_isar6 = t; > + t = cpu->isar.id_isar6; > + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); > + t = FIELD_DP32(t, ID_ISAR6, DP, 1); > + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); > + t = FIELD_DP32(t, ID_ISAR6, SB, 1); > + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); > + cpu->isar.id_isar6 = t; > > - t = cpu->isar.mvfr1; > - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ > - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ > - cpu->isar.mvfr1 = t; > + t = cpu->isar.mvfr1; > + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ > + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ > + cpu->isar.mvfr1 = t; > > - t = cpu->isar.mvfr2; > - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ > - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ > - cpu->isar.mvfr2 = t; > + t = cpu->isar.mvfr2; > + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ > + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ > + cpu->isar.mvfr2 = t; > > - t = cpu->isar.id_mmfr3; > - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ > - cpu->isar.id_mmfr3 = t; > + t = cpu->isar.id_mmfr3; > + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ > + cpu->isar.id_mmfr3 = t; > > - t = cpu->isar.id_mmfr4; > - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ > - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ > - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ > - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ > - cpu->isar.id_mmfr4 = t; > - } > -#endif > + t = cpu->isar.id_mmfr4; > + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ > + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ > + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ > + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ > + cpu->isar.id_mmfr4 = t; > } > +#endif Scary :) This is the if {} else {} removed, OK. Reviewed-by: Philippe Mathieu-Daudé > } > #endif > > @@ -2269,11 +2265,7 @@ static void arm_host_initfn(Object *obj) > > static const TypeInfo host_arm_cpu_type_info = { > .name = TYPE_ARM_HOST_CPU, > -#ifdef TARGET_AARCH64 > .parent = TYPE_AARCH64_CPU, > -#else > - .parent = TYPE_ARM_CPU, > -#endif > .instance_init = arm_host_initfn, > }; [...]